Semiconductor device

ABSTRACT

A semiconductor device is provided which has a memory provided with a peripheral device that can operate in a versatile manner, irrespective of combinations of storage capacity, numbers of banks and numbers of rows of memory cell arrays to be refreshed. The memory for storing various data, together with circuits to process a variety of signals, is mounted on one semiconductor chip. The memory includes a memory block in which a plurality of blocks each being made up of one memory cell array each having storage capacity of 1M bits or a plurality of blocks each being made up of one memory cell array and of a first and second sense amplifier between which the memory cell array is sandwiched, is arranged according to pre-set storage capacity of the memory block, and activating circuits which is so configured as to correspond to the block having a number satisfying a maximum settable storage capacity and outputs a variety of activating signals used to activate two or more blocks making up the memory block according to set storage capacity, the number of banks and the number of rows of memory cell arrays to be refreshed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and more particularly to the semiconductor device in which a system constructed by connecting, through buses and/or signal lines, a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), a plurality of signal processing circuits adapted to process a variety of signals or a like, is integrated into one semiconductor chip.

The present application claims priority of Japanese Patent Application No.2000-035930 filed on Feb. 14, 2000, which is hereby incorporated by reference.

2. Description of the Related Art

In recent years, as semiconductor devices such as an LSI (Large Scale Integrated circuit) or a like become highly integrated and as their packaging densities increase, a semiconductor on which one million or more transistors are mounted can be implemented. One example is a SOC (System On a Chip) in which a system constructed of a CPU, ROM, RAM, a plurality of digital signal processing circuits or a like each being connected through buses to each other, is incorporated into one semiconductor chip. For example, in a literature entitled “Embedded DRAM Macro for ASIC” (Shinji Miyano, Toshiba Review, Vol. 52, No.12. pp.15-18, 1997), a semiconductor device is disclosed in which a system constructed by connecting a DRAM (Dynamic Random Access Memory) having a large capacity memory and a digital signal processing circuit to process a variety of digital signals through buses is incorporated into one semiconductor chip. The semiconductor device of this kind has an advantage in that, since both the memory and digital signal processing circuit are formed on a same semiconductor chip, data can be transferred through buses each having a wider width for transmission and at a higher transmission speed between the memory and the digital signal processing circuit and also a mounting area on a printed circuit board (PCB) can be more reduced, unlike a case where the DRAM formed on an independent chip and encapsulated in an independent package is connected to LSIs containing digital signal processing circuits through pins and through patterns formed on a PCB.

However, since the SOC described above is large in scale, direct design at a transistor level is impossible. To solve this problem, system design to define operations or to decide configurations of a whole system, logical design to decide relations among functional blocks and to define operations within each of functional blocks in accordance with specifications decided by the system design, detail logic design to configure each of the functional blocks by combining logical devices such as NAND gates, NOR gates, latches, counters or a like and circuit design to decide characteristics of electronic circuits and elements so as to meet circuit specifications based on the logical design are sequentially performed, in stages, so that each of the CPUs, ROMs, RAMs or the plurality of digital signal processing circuits adapted to perform specified digital processing or a like can implement its desired functions as one functional block. Moreover, since the semiconductor device is generally expected to be embedded in various electronic devices, it is required that its development period is as short as possible. Therefore, in order to implement facilitation of the system design and shortening of development period, memories making up the SOC have to have general versatility which allows memories mounted on the SOC to be constructed by freely and flexibly combining a plurality of memory blocks containing memory cell arrays having specified memory capacities, sense amplifiers or a like, depending on desired storage capacities, the number of banks, the number of rows of memory cell arrays to be refreshed, or a like. In the above technical literature, there is also a description about such general versatility required in a unit configuration of a DRAM core.

However, since the memory making up the SOC is provided with not only memory blocks but also peripheral devices including input/output circuits used to input or output data to the memory blocks, control circuits generating various control signals used to input or output data to specified cells of the memory arrays making up the memory blocks, in order to achieve facilitation of system design and shortening of development period, it is required that such peripheral devices have such general versatility as described above. Though the above technical literature describes general versatility, however, it describes neither configurations of peripheral devices nor the general versatility required in the peripheral devices.

Thus, even if a system designer can design so that the memory making up the SOC is constructed by combing a plurality of memory blocks depending on desired storage capacities, the number of banks, the number of rows of memory cell arrays to be refreshed or the like, the system designer has to perform separate design of such peripheral devices, which causes a limitation on facilitation of the system design and shortening of development time.

SUMMARY OF THE INVENTION

In view of the above, it is an object of the present invention to provide a semiconductor device having a memory provided with a peripheral device which can operate in a versatile manner, irrespective of combinations of memory capacity, numbers of banks, numbers of rows of memory cell arrays to be refreshed or a like.

According to a first aspect of the present invention, there is provided a semiconductor device including:

a memory to store various data and to be embedded in one semiconductor chip together with circuits to process various signals, wherein the memory includes a memory block in which a plurality of blocks, being corresponded to pre-set storage capacity of the memory block, made up of a memory cell array having predetermined storage capacity and being constructed of a plurality of memory cells is arranged and an activating circuit configured so as to correspond to numbers of blocks satisfying maximum settable storage capacity which outputs a variety of activating signals used to activate a plurality of the blocks making up the memory block according to pre-set storage capacity and/or numbers of banks.

In the foregoing, a preferable mode is one wherein the activating circuit outputs, according to pre-set storage capacity and/or numbers of banks, a block selecting signal used to select any one of blocks making up the memory block, a row address latch signal used to temporarily latch a row address decoded by a row decoder which outputs a main-word activating signal to put a main-word line corresponding to the memory cell array in a selected state based on the decoded row address, a main-word timing control signal used to control timing with which the row decoder outputs the main-word activating signal and a sub-word activating signal used to activate a sub-word line of the memory cell array making up the corresponding block, to each of a plurality of the blocks making up the memory block.

Also, a preferable mode is one that wherein includes a control circuit which generates, according to pre-set storage capacity and/or numbers of banks and based on an address supplied from outside, a latch signal used to temporarily latch the block selecting signal, a first control signal used to control timing with which the row address latch signal is output, a second control signal used to control timing with which the activating circuit outputs the main-word timing control signal, a third control signal used to control timing with which the activating circuit outputs the sub-word activating signal, a capacity mode signal corresponding to pre-set storage capacity and a bank mode signal corresponding to numbers of banks and then feeds these signals to the activating circuit with specified timing, wherein the activating circuit, based on the latch signal, the first to third control signals, the capacity mode signal and the bank mode signal, generates the various activating signals.

Also, a preferable mode is one wherein the control circuit, when a test on the memory is executed, generates a test mode signal used to put all banks in a test mode, a test clock being a clock used in the test mode and a block forcedly-activating signal used to forcedly activate corresponding one block contained in the blocks and feeds these signals to the activating circuit, wherein the activating circuit, based on the test mode signal, the test clock and the block forcedly-activating signal, generates various activating signals.

Furthermore, a preferable mode is one wherein the memory cell array has a storage capacity of 1M bits and has a plurality of memory cells arranged in a matrix-like manner and in 512 rows×2048 columns form and wherein storage capacity that is allowed to be set includes any one of 1M, 2M, 4M and 8M bits and numbers of banks that are allowed to be set include any one of 1, 2 and 4.

According to a second aspect on the present invention, there is provided a semiconductor device including:

a DRAM (Dynamic Random Access Memory) to store various data and to be embedded in one semiconductor chip together with circuits to process various signals, wherein the DRAM includes a memory block in which a plurality of blocks, being corresponded to pre-set storage capacity of the memory block, made up of a memory cell array having predetermined storage capacity and being constructed of a plurality of memory cells is arranged and of first and second sense amplifiers constructed so as to sandwich the memory cell array and used to detect data read to a bit line from the memory cell making up the memory cell array and to amplify the data and an activating circuit configured so as to correspond to numbers of blocks satisfying maximum settable storage capacity which outputs a variety of activating signals used to activate a plurality of the blocks making up the memory block according to pre-set storage capacity, numbers of banks and numbers of rows of memory cell arrays to be refreshed representing numbers of rows of the memory cell arrays to be activated by one time refreshing processing.

In the foregoing, a preferable mode is one wherein the activating circuit outputs, according to pre-set storage capacity, numbers of banks and numbers of rows of memory cell arrays, a block selecting signal used to select any one of blocks making up the memory block, a row address latch signal used to temporarily latch a row address decoded by a row decoder which outputs a main-word activating signal to put a main-word line corresponding to the memory cell array in a selected state, based on the decoded row address, a main-word timing control signal used to control timing with which the row decoder outputs the main-word activating signal, a sub-word activating signal used to activate a sub-word line of the memory cell array making up the corresponding block and a sense amplifier activating signal used to activate two sense amplifiers making up the corresponding block, to each of a plurality of the blocks making up the memory block.

Also, a preferable mode is one that wherein includes a control circuit which generates, according to pre-set storage capacity, numbers of banks and numbers of rows of memory cell arrays to be refreshed and based on an address supplied from outside, a latch signal used to temporarily latch the block selecting signal, a first control signal used to control timing with which the row address latch signal is output, a second control signal used to control timing with which the activating circuit outputs the main-word timing control signal, a third control signal used to control timing with which the activating circuit outputs the sub-word activating signal, a fourth control signal used to control timing with which the activating circuit outputs the sense amplifier activating signal, a capacity mode signal corresponding to pre-set storage capacity, a bank mode signal corresponding to numbers of banks, a refresh mode signal corresponding to pre-set numbers of rows of memory cell arrays to be refreshed and then feeds these signals to the activating circuit with specified timing, wherein the activating circuit, based on the latch signal, the first to fourth control signals, the capacity mode signal, the bank mode signal and the refresh mode signal, generates various activating signals.

Also, a preferable mode is one wherein the activating circuit includes a refresh decoder to decode data obtained by combining higher-order bits contained in the refresh mode signal with those contained in the row address and to generate a block activating designation signal used to designate the block to be activated and a block activating section mounted in numbers corresponding to numbers of blocks satisfying maximum settable capacity, to generate, based on the latch signal, a reversed latch signal obtained by reversing the latch signal, the first to fourth control signals, the capacity mode signal, the bank mode signal and the refresh mode signal, according to pre-set storage capacity, numbers of banks and numbers of rows of memory cell arrays to be refreshed, with specified timing, the block selecting signal and generates the row address latch signal, the main-word timing control signal, the sub-word activating signal and the sense amplifier activating signal.

Also, a preferable mode is one wherein the block activating section includes a block selecting signal generating circuit which generates, based on the block activating designation signal, the latch signal, the reversed latch signal, the refresh mode signal and the bank mode signal, a block selecting signal used to designate the corresponding block, a row address latch signal generating circuit which generates, based on the first control signal and the block selecting signal, the row address latch signal and feeds it to corresponding one contained in the blocks and an activating signal generating circuit which generates, based on the second to fourth control signals and the block selecting signal, the sub-word activating signal and the sense amplifier activating signal and the main-word timing control signal and feeds these signals to corresponding blocks.

Also, a preferable mode is one wherein the control circuit, when a test on the memory is executed, generates a test mode signal used to put all banks in a test mode, a test clock being a clock used in the test mode and a block forcedly-activating signal used to forcedly activate corresponding one block contained in the blocks and feeds these signals to the activating circuit, wherein the activating circuit, based on the test mode signal, the test clock and the block forcedly-activating signal, generates the various activating signals.

Furthermore, a preferable mode is one wherein the memory cell array has a storage capacity of 1M bits and has a plurality of memory cells arranged in a matrix-like manner and in 512 rows×2048 columns form and wherein storage capacity that is allowed to be set includes any one of 1M, 2M, 4M and 8M bits, numbers of banks that are allowed to be set include any one of 1, 2 and 4 and numbers of rows of memory cell arrays to be refreshed that are allowed to be set include any one of 512, 2¹⁰, 2¹¹ and 2¹².

With the above configuration, since the memory or the DRAM embedded in the one semiconductor chip of the present invention is provided with the memory block in which a plurality of blocks each being made up of one memory cell array having predetermined storage capacity or a plurality of blocks each being made up of one memory cell array and of first and second sense amplifiers between which the memory cell array is sandwiched, is arranged according to pre-set storage capacity of the memory block and with activating circuits so configured as to correspond to the block having the number satisfying the maximum settable storage capacity and output a variety of activating signals used to activate the two or more blocks making up the memory block according to the pre-set storage capacity, the number of banks and the number of rows of memory cell arrays to be refreshed, system designer, even when combinations of the storage capacity, the number of banks and the number of rows of memory cell arrays to be refreshed are changed, can freely and easily perform system design of the memory of the semiconductor device. This also allows system design of the semiconductor device to be made easier and development period of the semiconductor device to be shortened.

With another configuration as above, since the activating circuit, according to the pre-set storage capacity and/or the number of banks and for each of the two or more blocks, generates the row address latch signal used to temporarily hold the row address decoded by the row decoder and the block selecting signal used to select one of blocks making up the memory block and since the control circuit generates the latch signal used to temporarily hold the block selecting signal, it is possible to perform multi-banking operations in which a plurality of blocks belonging to a plurality of banks is simultaneously activated.

With still another configuration as above, since the control circuit generates the test mode signal, test clock and block forcedly-activating signal and the activating circuit, based on the test mode signal, test clock and block forcedly-activating signal, generates various activating signals, it is possible to execute the reliability test on the memory.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic block diagram showing configurations of a memory making up a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a schematic block diagram showing one example of configurations of a memory block making up the memory according to the embodiment of the present invention;

FIG. 3 is a schematic circuit diagram showing one example of configurations of a row decoder employed in the memory according to the embodiment of the present invention;

FIG. 4 is a schematic block diagram showing configurations of an activating circuit employed in the memory according to the embodiment of the present invention;

FIG. 5 is a schematic circuit diagram showing one example of configurations of a refresh decoder employed in the memory according to the embodiment of the present invention;

FIG. 6 is a schematic block diagram showing configurations of one block activating section employed in the memory according to the embodiment of the present invention;

FIG. 7 is a schematic block diagram showing one example of configurations of a block selecting signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 8 is a schematic block diagram showing one example of configurations of a row address latch signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 9 is a schematic block diagram showing one example of configurations of an activating signal generating circuit employed on the memory according to the embodiment of the present invention;

FIG. 10 is a schematic block diagram showing configurations of another block activating section employed in the memory according to the embodiment of the present invention;

FIG. 11 is a schematic block diagram showing one example of configurations of another block selecting signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 12 is a schematic block diagram showing one example of configurations of another row address latch signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 13 is a schematic block diagram showing one example of configurations of another activating signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 14 is a schematic block diagram showing configurations of another block activating section employed in the memory according to the embodiment of the present invention;

FIG. 15 is a schematic block diagram showing one example of configurations of another block selecting signal generating employed in the memory according to the embodiment of the present invention;

FIG. 16 is a schematic block diagram showing one example of configurations of another row address latch signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 17 is a schematic block diagram showing one example of configurations of another activating signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 18 is a schematic block diagram showing configurations of another block activating section employed in the memory according to the embodiment of the present invention;

FIG. 19 is a schematic block diagram showing one example of configurations of another block selecting signal generating employed in the memory according to the embodiment of the present invention;

FIG. 20 is a schematic block diagram showing one example of configurations of another row address latch signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 21 is a schematic block diagram showing one example of configurations of another activating signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 22 is a schematic block diagram showing configurations of another block activating section employed in the memory according to the embodiment of the present invention;

FIG. 23 is a schematic block diagram showing one example of configurations of another block selecting signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 24 is a schematic block diagram showing one example of configurations of another row address latch signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 25 is a schematic block diagram showing one example of configurations of another activating signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 26 is a schematic block diagram showing configurations of another block activating section employed in the memory according to the embodiment of the present invention;

FIG. 27 is a schematic block diagram showing one example of configurations of another block selecting signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 28 is a schematic block diagram showing one example of configurations of another row address latch signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 29 is a schematic block diagram showing one example of configurations of another activating signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 30 is a schematic block diagram showing configurations of another block activating section employed in the memory according to the embodiment of the present invention;

FIG. 31 is a schematic block diagram showing one example of configurations of another block selecting signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 32 is a schematic block diagram showing one example of configurations of another row address latch signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 33 is a schematic block diagram showing one example of configurations of another activating signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 34 is a schematic block diagram showing configurations of another block activating section employed in the memory according to the embodiment of the present invention;

FIG. 35 is a schematic block diagram showing one example of configurations of another block selecting signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 36 is a schematic block diagram showing one example of configurations of another row address latch signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 37 is a schematic block diagram showing one example of configurations of another activating signal generating circuit employed in the memory according to the embodiment of the present invention;

FIG. 38 is a timing chart briefly explaining normal operations of a DRAM according to the embodiment of the present invention;

FIG. 39 is a timing chart explaining, in detail, normal operations of the DRAM in which 8M bits are set as storage capacity, 4 is set as number of banks and 1K is set as number of rows of memory cell arrays to be refreshed according to the embodiment of the present invention;

FIG. 40 is a timing chart explaining, in detail, normal operations of the DRAM in which 8M bits are set as the storage capacity, 4 is set as the number of banks and 1K is set as the number of rows of memory cell arrays to be refreshed according to the embodiment of the present invention;

FIG. 41 is a timing chart explaining, in detail, normal operations of the DRAM in which 8M bits are set as the storage capacity, 4 is set as the number of banks and 1K is set as the number of rows of memory cell arrays to be refreshed according to the embodiment of the present invention;

FIG. 42 is a timing chart explaining, in detail, multi-banking operations of the DRAM in which 8M bits are set as the storage capacity, 4 is set as the number of banks and 1K is set as the number of rows of memory cell arrays to be refreshed according to the embodiment of the present invention;

FIG. 43 is a timing chart explaining, in detail, multi-banking operations of the DRAM in which 8M bits are set as the storage capacity, 4 is set as the number of banks and 1K is set as the number of rows of memory cell arrays to be refreshed according to the embodiment of the present invention;

FIG. 44 is a timing chart explaining, in detail, multi-banking operations of the DRAM in which 8M bits are set as the storage capacity, 4 is set as the number of banks and 1K is set as the number of rows of memory cell arrays to be refreshed according to the embodiment of the present invention;

FIG. 45 is a timing chart briefly explaining testing operations of the DRAM according to the embodiment of the present invention;

FIG. 46 is a timing chart explaining, in detail, multi-banking operations of the DRAM in which 2M bits are set as the storage capacity, 1 is set as the number of banks and 1K is set as the number of rows of memory cell arrays to be refreshed according to the embodiment of the present invention;

FIG. 47 is a timing chart explaining, in detail, multi-banking operations of the DRAM in which 2M bits are set as the storage capacity, 1 is set as the number of banks and 1K is set as the number of rows of memory cell arrays to be refreshed according to the embodiment of the present invention;

FIG. 48 is a timing chart explaining, in detail, multi-banking operations of the DRAM in which 2M bits are set as the storage capacity, 1 is set as the number of banks and 1K is set as the number of rows of memory cell arrays to be refreshed according to the embodiment of the present invention; and

FIG. 49 is a table showing combinations of the storage capacity, the number of banks and the number of rows of memory cell arrays to be refreshed that can be applied to the embodiment and relations among capacity mode signals, bank mode signals and refresh mode signals that can be applied to the embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Best modes of carrying out the present invention will be described in further detail using various embodiments with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram showing configurations of a memory making up a semiconductor device according to an embodiment of the present invention.

The memory of the embodiment chiefly includes a memory block 1 being a DRAM having a storage capacity of 8M bits and numbers of rows of memory cell arrays to be refreshed being 1K (=2¹⁰) which represent the number of rows of memory cell arrays (hereinafter the memory cell array being referred to as an “MCA”) to be activated by one time refreshing processing and being made up of four banks, an input/output circuit 2, a control circuit 3, an activating circuit 4, column decoder groups 5 ₁ to 5 ₄ and row decoder groups 6 ₁ to 6 ₄.

The memory block 1, as shown in FIG. 2, is made up of four banks 7 ₁ to 7 ₄, each bank having a storage capacity of 2M bits. Each of the bank 7 ₁ to 7 ₄ chiefly includes two MCAs 8 ₁ and 8 ₂ and four sense amplifiers (hereinafter the sense amplifier being referred to as an “SA”) 9 ₁₁, 9 ₁₂, 9 ₂₁ and 9 ₂₂. Each of the MCAs 8 ₁ and 8 ₂ has a storage capacity of 1M bits and is made up of a plurality of memory cells (512 rows×2048 columns) arranged in a matrix-like form. Each of the MCA 8 ₁ and 8 ₂ is generally called a “512 refresh array”. The MCAs 8 ₁ and 8 ₂ are mounted in a manner so as to be sandwiched between the SA 9 ₁₁ and SA 9 ₁₂ and between the SA 9 ₂₁ and SA 9 ₂₂, respectively. Each of the SA 9 ₁₁, SA 9 ₁₂, SA₂₁ and SA 9 ₂₂ detects data read through bit lines from the memory cells contained in the MCA 8 ₁ or the MCA 8 ₂ selected by the column decoder making up the column decoder groups 5 ₁ to 5 ₄ and amplifies the detected data. Hereinafter, the one MCA and the two SAs between which the one MCA is sandwiched are referred to as a “block” as a whole.

The input/output circuit 2 shown in FIG. 1 includes chiefly an input/output amplifier (not shown), a data input/output circuit (not shown) and a data input/output bus (not shown) adapted to connect the input/output amplifier to the data input/output circuit. The input/output amplifier is mounted on each of the banks 7 ₁ to 7 ₄ and chiefly includes a data amplifier (not shown) adapted to amplify data fed through an input/output line (not shown) after the data has been detected and amplified by each of the SA 9 ₁₁, SA 9 ₁₂, SA 9 ₂₁ and SA 9 ₂₂ and a write amplifier (not shown) adapted to amplify data fed through the data input/output bus from the data input/output circuit.

The data input/output circuit is also mounted on each of the banks 7 ₁ to 7 ₄ and feeds data input from a data input/output terminal (not shown) through the data input/output bus and, at the same time, sequentially outputs data fed through the data input/output bus from the input/output amplifier from the data input/output terminal.

The control circuit 3, when being triggered by an address signal CAD fed from outside, outputs various signals, with specified timing, depending on the storage capacity (8M bits in this embodiment), the number of banks (4 banks in this embodiment) and the number of rows of memory cell arrays to be refreshed (1K in this embodiment) which are all set by a system designer. That is, the control circuit 3 outputs latch signals LT₁ to LT₄ each being used to temporarily latch a block selecting signal BS which is generated in the activating circuit 4 and which is used to select any one block out of the blocks making up the memory block 1 and reversed latch signals /LT₁ to /LT₄ obtained by reversing the latch signals LT₁ to LT₄.

The control circuit 3 also outputs first control signals FIRC₁ to FIRC₄ used to control timing with which the row decoder 10 making up the row decoder groups 6 ₁ to 6 ₂ outputs row address latch signals RLT₁ to RLT₈ which are output from the activating circuit 4 and are used to temporarily latch the decoded row address, second Control signals SECC₁ to SECC₄ used to control timing with which the activating circuit 4 outputs main-word timing control signals MTC₁ to MTC₈ used to control timing with which the row decoder 10 making up row decoder groups 6 ₁ to 6 ₄ outputs a main-word line activating signal MWAT to activate main word-lines of the corresponding MCA, third control signals THIC₁ to THIC₄ used to control timing with which sub-word line activating signals SWAT₁ to SWAT₈ are output, which are output from the activating circuit 4 and are used to activate the sub-word line of the MCA making up any one of blocks contained in the memory block 1 and fourth control signals FORC₁₁ to FORC₁₄ and FORC₂₁ to FORC₂₄, used to control timing with which two kinds of SA activating signals, SAAT₁₁ to SAAT₁₈ making up one kind and SAAT₂₁ to SAAT₂₈ making up the other kind are output, both of which are output from the activating circuit 4 and are used to activate two SAs making up any one of blocks contained in the memory block 1.

Moreover, the control circuit 3 outputs capacity mode signals CM₂, CM₄ and CM₈ which go high or low depending on the storage capacity (any one of 1M bits, 2M bits, 4M bits and 8M bits) pre-set by the system designer, bank mode signals BM₁, BM₂ and BM₄ which go high or low depending on the number of banks (any one of one, two or four banks) pre-set by the system designer and refresh mode signals RM₀₅, RM₁₀, RM₂₀ and RM₄₀ which go high or low depending on the number of rows of memory cell arrays to be refreshed (any one of 512, 1K, 2K [=2 ¹¹] and 4K [=2¹²]). The control circuit 3 also feeds 11-bit column address signals CAD out of the address signals AD supplied from outside to the column decoder groups 5 ₁ to 5 ₄ and maximum 12-bit row address signals RAD (RAD₁ to RAD₁₂) to the row decoder groups 6 ₁ to 6 ₄ and, at the same time, feeds row address higher-order bit signals RAD₁ to RAD₁₂ being higher-order 3 bit row address signal RAD and reversed row address higher-order signals /RAD₁₀ to /RAD₁₂ obtained by reversing the signals RAD₁₀ to RAD₁₂ to the activating circuit 4.

The control circuit 3, when a reliability test on the DRAM such as an analysis on defects is executed, in order to perform screening by applying a voltage being higher than that normally used to all word lines of all the banks 7 ₁ to 7 ₄, outputs a high-level test mode signal TM used to put all the banks 7 ₁ to 7 ₄ in the reliability test mode, a test clock TCK being a clock used in the test mode and block forcedly-activating signals BFAT₁ to BFAT₈ each sequentially rising to go high on the test clock TCK and, irrespective of a state of block selecting signal BS, forcedly activating corresponding one of the blocks making up the memory block 1.

The activating circuit 4, based on the latch signals LT₁ to LT₄, reversed latch signals /LT₁ to /LT₄, first control signals FIRC₁ to FIRC₄, second control signals SECC₁ to SECC₄, third control signals THIC₁ to THIC₄, fourth signals FORC₁₁ to FORC₁₄ and FORC₂₁ to FORC₂₄, capacity mode signals CM₂, CM₄ and CM₈, bank mode signals BM₁, BM₂ and BM₄, refresh mode signals RM₀₅, RM₁₀, RM₂₀ and RM₄₀, row address higher-bit signals RAD₁₀ to RAD₁₂, reversed row address higher-bit signals /RAD₁₀ to /RAD₁₂, test signal TM, test clock a TCK and block forcedly-activating signals BFAT₁ to BFAT₈ all of which are fed from the control circuit 3, generates the block selecting signal BS, with specified timing, depending on storage capacities, the number of banks and the number of rows of memory cell arrays to be refreshed and, at the same time, row address latch signals RLT₁ to RLT₈, main-word timing control signals MTC₁ to MTC₅, sub-word line activating signals SWAT₁ to SWAT₈ and SA activating signals SAAT₁₁ to SAAT₁₈ and SAAT₂₁ to SAAT₂₈. Configurations of the activating circuit 4 will be described later in detail.

Each of the column decoder groups 5 ₁ to 5 ₄ is mounted in a manner so as to correspond to each of the banks 7 ₁ to 7 ₄ making up the memory block 1, decodes the column address signal CAD fed from the control circuit 3 and is provided with a plurality of column decoders adapted to output column selecting signals used to select a plurality of column selecting switches adapted to put the SAs 9 ₁₁, 9 ₁₂, 9 ₂₁ and 9 ₂₂ in a selected state, each of which is connected to the corresponding bit line of the MCA 8 ₁ and 8 ₂ making up each of the banks 7 ₁ to 7 ₄. Each of the row decoder groups 6 ₁ to 6 ₄ is mounted in a manner so as to correspond to each of the banks 7 ₁ to 7 ₄ making up the memory block 1, decodes the row address signal RAD fed from the control circuit 3 and is provided with a plurality of row decoders 10 each temporarily latching the decoded row address signal by using one of the row address latch signals RLT₁ to RLT₈ supplied from the activating circuit 4 and then, with timing controlled by main-word timing control signals MTC₁ to MTC₈ to be fed from the activating circuit 4, output the main-word activating signal MWAT used to put the corresponding main-word lines of the MCA 8 ₁ to 8 ₂ in a selected state.

FIG. 3 is a schematic circuit diagram showing one example of configurations of a row decoder 10 employed in the memory according to the embodiment.

The row decoder 10 of the embodiment includes a decoder 11 adapted to decode fourth to ninth bit address signals RAD₄ to RAD₈ out of the maximum 12-bit row address signals RAD fed from the control circuit 3, an n-channel MOS transistor 12 which is turned ON by the high-level row address latch signals RLT₁ to RLT₈ fed from the activating circuit 4 and allows data output from the decoder 11 to be transmitted through, a latch 13 adapted to reverse data signals output from the decoder 11 and to temporarily latch the data signals when the row address latch signals RLT₁ to RLT₈ are changed to go low to cause the n-channel MOS transistor 12 to turned OFF and a NAND gate 14 adapted to output data read from the latch 13 as the main-word activating signal MWAT when the high-level main-word timing control signals MTC₁ to MTC₈ are fed from the activating circuit 4. Thus, since the latch 13 is incorporated, even if the row address is changed later, the memory block 1 can remain activated.

Next, configurations of the activating circuit 4 will be described by referring to FIG. 4 to FIG. 37. The activating circuit 4, as shown in FIG. 4, chiefly includes a refresh decoder 15 and block activating sections 16 ₁ to 16 ₈.

The refresh decoder 15 decodes signals obtained by combining refresh mode signals RM₁₀, RM₂₀ and RM₄₀ to be fed from the control circuit 3 with row address higher-bit signals RAD₁₀ to RAD₁₂ and reversed row address higher-bit signals /RAD₁₀ to /RAD₁₂ and produces block activating designation signals ATD₁ to ATD₁₄ used to designate a block to be activated. Detailed configurations of the refresh decoder 15 will be explained later. Each of the block activating sections 16 ₁ to 16 ₈ generates a signal required to activate each of corresponding blocks. The block activating sections 16 ₁ to 16 ₈ produce block selecting signals BS, based on the latch signals LT₁ to LT₄ to be fed from the control circuit 3, reversed latch signals /LT₁ to /LT₄, first control signals FIRC₁ to FIRC₄, second control signals SECC₁ to SECC₄, third control signals THIC₁ to THIC₄, fourth control signals FORC₁₁ to FORC₁₄ and FORC₂₁ to FORC₂₄, capacity mode signals CM₂, CM₄ and CM₈, bank mode signals BM₁, BM₂ and BM₄, refresh mode signal RM₀₅, test mode signal TM, test clock TCK and block forcedly-activating signals BFAT₁ to BFAT₈, depending on the storage capacity, the number of banks and the number of rows of memory cell arrays to be refreshed, all of which are set by the system designer, with specified timing and, at the same time, row address latch signals RLT₁ to RLT₈, main-word timing control signals MTC₁ to MTC₈, sub-word activating signals SWAT₁ to SWAT₈, SA activating signals SAAT₁₁ to SAAT₁₈ and SAAT₂₁ to SAAT₂₈ and outputs them. Configurations of the block activating sections 16 ₁ to 16 ₈ will be explained later.

Next, configurations of the refresh decoder 15 will be described by referring to FIG. 5. The refresh decoder 15 includes decoders 17 ₁ to 17 ₁₄. The decoder 17 ₁ decodes signals obtained by combining the refresh mode signal RM₁₀, which goes high when the system designer sets the number of rows of memory cell arrays to be refreshed at 1k, with reversed row address higher-bit signal /RAD₁₀ and produces the block activating designation signal ATD₁ used to designate the block to be activated. The decoder l7 ₂decodes signals obtained by combining the refresh mode signal RM₁₀ with the row address higher-bit signal RAD₁₀ and generates the block activating designation signal ATD₂ used to designate the block to be activated. The decoder 17 ₃ decodes signals obtained by combining refresh mode signal RM₂₀, which goes high when the system designer sets the number of rows of memory cell arrays to be refreshed at 2k, with the reversed row address higher-bit signal /RAD₁₀ and with reversed row address higher-bit signal /RAD₁₁ and generates the block activating designation signal ATD₃ used to designate the block to be activated. The decoder 17 ₄ decodes signals obtained by combining the refresh mode signal RM₂₀ with the row address higher-bit signal RAD₁₀ and with the reversed row address higher-bit signal /RAD₁₁ and generates the block activating designation signal ATD₄ used to designate the block to be activated. The decoder 17 ₅ decodes signals obtained by combining the refresh mode signal RM₂₀ with reversed row address higher-bit signal /RAD₁₀ and with row address higher-bit signal RAD₁₁ and generates the block activating designation signal ATD₅ used to designate the block to be activated. The decoder 17 ₆ decodes signals obtained by combining the refresh mode signal RM₂₀ with the row address higher-bit signal RAD₁₀ and with the row address higher-bit signal RAD₁₁ and generates the block activating designation signal ATD₆ used to designate the block to be activated. The decoder 17 ₇ decodes signals obtained by combining the refresh mode signal RM₄₀, which goes high when the system designer sets the number of rows of memory cell arrays to be refreshed at 4 k, with the reversed row address higher-bit signal /RAD₁₀, with the reversed row address higher-bit signal /RAD₁₁ and with the reversed row address higher-bit signal /RAD₁₂ and generates the block activating designation signal ATD₇ used to designate the block to be activated. The decoder 17 ₈ decodes signals obtained by combining the refresh mode signal RM₄₀ with the row address higher-bit signal RAD₁₀, with the reversed row address higher-bit signal /RAD₁₁ and with the reversed row address higher-bit signal /RAD₁₂ and generates the block activating designation signal ATD₈ used to designate the block to be activated. The decoder 17 ₉ decodes signals obtained by combining the refresh mode signal RM₄₀ with the reversed row address higher-bit signal /RAD₁₀, with the row address higher-bit signal RAD₁₁ and with the reversed row address higher-bit signal /RAD₁₂ and generates the block activating designation signal ATD₉ used to designate the block to be activated. The decoder 17 ₁₀ decodes signals obtained by combining the refresh mode signal RM₄₀ with the row address higher-bit signal RAD₁₀, with the row address higher-bit signal RAD₁₁ and with the reversed row address higher-bit signal /RAD₁₂ and generates the block activating designation signal ATD₁₀ used to designate the block to be activated. The decoder 17 ₁₁ decodes signals obtained by combining the refresh mode signal RM₄₀ with the reversed row address higher-bit signal /RAD₁₀, with the reversed row address higher-bit signal /RAD₁₁ and with the row address higher-bit signal RAD₁₂ and generates the block activating designation signal ATD₁₁ used to designate the block to be activated. The decoder 17 ₁₂ decodes signals obtained by combining the refresh mode signal RM₄₀ with the row address higher-bit signal RAD₁₀, with the reversed row address higher-bit signal /RAD₁₁ and with the row address higher-bit signal RAD₁₂ and generates the block activating designation signal ATD₁₂ used to designate the block to be activated. The decoder 17 ₁₃ decodes signals obtained by combining the refresh mode signal RM₄₀ with the reversed row address higher-bit signal /RAD₁₀, with the row address higher-bit signal RAD₁₁ and with the row address higher-bit signal RAD₁₂ and generates the block activating designation signal ATD₁₃ used to designate the block to be activated. The decoder 17 ₁₄ decodes signals obtained by combining the refresh mode signal RM₄₀ with the row address higher-bit signal RAD₁₀, with the row address higher-bit signal RAD₁₁ and with the row address higher-bit signal RAD₁₂ and generates the block activating designation signal ATD₁₄ used to designate the block to be activated.

Next, configurations of the block activating sections 16 ₁ to 16 ₈ will be described by referring to FIG. 6 to FIG. 37. The block activating section 16 ₁ includes, as shown in FIG. 6, a block selecting signal generating circuit 18 ₁, a row address latch signal generating circuit 19 ₁ and an activating signal generating circuit 20 ₁. The block selecting signal generating circuit 18 ₁, based on the block activating designation signals ATD₁, ATD₃ and ATD₇ to be supplied from the refresh decoder 15, the latch signal LT₁ and reversed latch signal /LT₁ to be supplied from the control circuit 3, the refresh mode signal RM₀₅, and based on bank mode signals BM₁, BM₂ and BM₄, generates any one of the block selecting signal BS₁₁₁ used to activate the first block, if a memory block 1 is made up of one bank, using the whole blocks belonging to the one bank, a block selecting signal BS₁₁₂ used to activate the first block, when the memory block 1 is made up of four banks, using the whole blocks belonging to the first bank and a block selecting signal BS₁₁₄ used to activate the first block, if the memory block 1 is made up of four banks, using the whole blocks belonging to the first bank.

FIG. 7 is a schematic block diagram showing one example of configurations of a block selecting signal generating circuit 18 ₁ employed in the memory according to the embodiment. The block selecting signal generating circuit 18 ₁ includes an OR gate 21 having two inputs, an OR gate 22 having three inputs, an OR gate 23 having four inputs, NAND gates 24 to 26 each having two inputs, transfer gates 27 to 29, latches 30 to 32 and inverters 33 to 35. When either of the refresh mode signal RM₀₅ which goes high when the system designer sets the number of rows of memory cell arrays to be refreshed at 512 or the high-level block activating designation signal ATD₁ which is produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 1k and when a high-level reversed row address higher-bit signal /RAD₁₀ is fed to the OR gate 21, a high-level signal is output from the OR gate 21. Therefore, when the output high-level signal is input to the NAND gate 24 and if the high-level bank mode signal BM₄ to be supplied when the system designer sets the number of banks at four, has been fed to the NAND gate 24, a low-level signal is output from the NAND gate 24, which passes through the transfer gate 27 being turned ON and is reversed by the latch 30 to go high and is again reversed by the inverter 33 to go low and is then output as the low-level block selecting signal BS₁₁₄ used to select the first block, if the memory block 1 is made up of four banks, by using the whole blocks belonging to the first bank. Then, when the high-level latch signal LT₁ and the low-level reversed latch signal /LT₁ used to temporarily latch the block selecting signal BS to be supplied to all blocks belonging to the first bank are fed from the control circuit 3 to the transfer gate 27, the transfer gate 27 is turned OFF. While the transfer gate 27 is in an OFF state, a state of the block selecting signal BS₁₁₄ obtained before being reversed is being latched by the latch 30. Moreover, an aim of temporarily holding the state of the block selecting signal BS₁₁₄ obtained before being reversed in the latch 30 by using the high-level latch signal LT₁ and the low-level reversed latch signal /LT₁ is to prevent the block being now operated from becoming inactivated even when other blocks are activated at later time compared with the block being now operated. The latches 31 and 32 are mounted because of the same reasons as above.

When the high-level refresh mode signal RM₀₅ and either of the high-level block activating designation signal ATD₃ or the block activating designation signal ATD₃ which is produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 2k and when the high-level reversed row address higher-bit signal /RAD₁₀ and the high-level reversed row address higher-bit signal /RAD₁₁ are supplied, are fed to the OR gate 22, a high-level signal is output from the OR gate 22. Therefore, if the bank mode signal BM₂ to be supplied when the system designer sets the number of banks at two, has been fed to the NAND gate 25, a low level signal is output from the NAND gate 25, which passes through the transfer gate 28 and is reversed by the latch 31 to go high and is again reversed by the inverter 34 to go low and then is output as the low-level block selecting signal BS₁₁₂ used to select the first block, if the memory block 1 is made up of two banks, by using the whole blocks belonging to the first bank. Then, when the high-level latch signal LT₁ and the low-level reversed latch signal /LT₁ are fed from the control circuit 3 to the transfer gate 28, the transfer gate 28 is turned OFF. While the transfer gate 28 is in an OFF state, a state of the block selecting signal BS₁₁₂ obtained before being reversed is being latched by the latch 31.

When the high-level refresh mode signal RM₀₅ and any one of the block activating designation signal ATD₁, block activating designation signal ATD₃ and the block activating designation. signal ATD₇ produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 4k and when the high-level reversed row address higher-bit signal /RAD₁₀, the high-level reversed row address higher-bit signal /RAD₁₁ and the high-level reversed row address higher-bit signal ATD₇ are supplied, are fed to the OR gate 23, a high-level signal is output from the OR gate 23. Therefore, if the bank mode signal BM₁ produced because the system designer had set the number of banks at one, has been fed to the NAND gate 26, a low level signal is output from the NAND gate 26, which passes through the transfer gate 29 and is reversed by the latch 32 to go high and is again reversed to go low by the inverter 35 and is then output as the low-level block selecting signal BS₁₁₁ used to select the first block, if the memory block 1 is made up of one bank, by using the whole blocks belonging to the bank. Then, when the high-level latch signal LT₁ and the low-level reversed latch signal /LT₁ are fed from the control circuit 3 to the transfer gate 29, the transfer gate 29 is turned OFF. While the transfer gate 29 is in an OFF state, a state of the block selecting signal BS₁₁₁ obtained before being reversed is latched by the latch 32. Moreover, when the system designer sets the number of rows of memory cell arrays to be refreshed at 512, the high-level refresh mode signal RM₀₅ is fed and even when the system designer sets the number of banks to any value, one of the block selecting signals BS is output. This is because no block activating designation signal ATD is produced, as is understood from FIG. 5.

The row address latch signal generating circuit 19 ₁, based on the first control signal FIRC₁ fed from the control circuit 3, test mode signal TM, block forcedly-activating signal BFAT₁, and block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄, generates the row address latch signal RLT₁ used to temporarily latch the row address decoded by the row decoder 10 (see FIG. 3) and to feeds it to the first block.

FIG. 8 is a schematic block diagram showing one example of configurations of the row address latch signal generating circuit 19 ₁. The row address latch signal generating circuit 19 ₁ includes inverters 36 and 37, OR gates 38 to 41 each having two inputs, AND gate 42 having three inputs and NAND gate 43 each having two inputs. In a state where all the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₁ and, at the same time, the first control signal FIRC₁ used to control timing of outputting the row address latch signal RLT₁ to the first bank is fed as the low-level signal, since a high-level signal is output from any one of the OR gates 38 to 41, a high-level signal is output from the AND gate 42. Moreover, normally, the test mode signal TM and the block forcedly-activating signal BFAT₁ are fed as low-level signals. Therefore, in this state, the low-level row address latch signal RLT₁ is output from the NAND gate 43. Next, even when any one of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ is fed as the low-level signal, if the first control signal FIRC₁ remains at a low level, no changes occur. Then, when the first control signal FIRC₁ changes to go high, since any one of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ has been changed to be at a high level, a low-level signal is output from the OR gate 38 to 41 to which any one of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ has been fed. Since this causes the AND gate 42 to output a low-level signal, the row address latch signal RLT₁ is output from the NAND gate 43 and is then fed to the first block. That is, after the row address signal generating circuit 19 ₁ has been selected from 8 pieces of the row address signal generating circuits 19 ₁ to 19 ₈ by any one of the high-level block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄, the high-level row address latch signal RLT₁ is output with timing in which the first control signal FIRC₁ changes to go high and is fed to the first block. Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ and the first control signal FIRC₁, with timing in which the block forcedly-activating signal BFAT₁ changes to go high, the high-level row address latch signal RLT₁ is output.

The activating signal generating circuit 20 ₁ shown in FIG. 6, based on the second control signal SECC₁, third control signal THIC₁, fourth control signals FORC₁₁ and FORC₂₁, test mode signal TM, test clock TCK and block forcedly-activating signal BFAT₁ all of which are fed from the control circuit 3, and based on the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ fed from the block selecting signal generating circuit 18 ₁, generates the sub-word activating signal SWAT₁ used to activate the sub-word line of the MCA making up the first block contained in the memory block 1, two kinds of SA activating signals SAAT₁₁ and SAAT₂₁ used to activate two SAs making up the first block contained in the memory block 1 and the main-word timing control signal MTC₁ used to control timing with which the row decoder 10 outputs the main-word activating signal MWAT and then feeds them to the first block.

FIG. 9 is a schematic block diagram showing one example of configurations of the activating signal generating circuit 20 ₁ employed in the memory according to the embodiment. The activating signal generating circuit 20 ₁ of the embodiment includes inverters 44 to 48, OR gates 49 to 61, each having two inputs, AND gate 62 having three inputs, NAND gate 63 having two inputs, SR latch 64, NAND gate 65 having four inputs and NAND gates 66 and 67 each having three inputs. In a state where all the block selecting signals BS₁₁₁, BS,₁₁₂ and BS₁₁₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₁ and, at the same time, the second control signal SECC₁ used to control timing with which the main-word timing control signal MTC₁ is output to the first bank is fed as the low-level signal, since a high-level signal is output from any one of the OR gates 49 to 51, a high-level signal is output from the AND gate 62. Normally, all the test mode signal TM and block forcedly-activating signal BFAT₁ are fed as low-level signals. Therefore, in this state, the low-level main-word timing control signal MTC₁ is output from the NAND gate 63. Next, even when any one of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ is fed as low-level signals, if the second control signal SECC₁ remains at a low level, no changes occur. Then, when the second control signal SECC₁ changes to go high, since one of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which any one of the block selecting signals has BS₁₁₁, BS₁₁₂ and BS₁₁₄ been fed. This causes the AND gate 62 to output a low-level signal and the NAND gate 63 to output the high-level main-word timing control signal MTC₁ which is then fed to the first block. That is, after the activating signal generating circuit 20 ₁ has been selected from 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄, the high-level main-word timing control signal MTC₁ is output with timing in which the second control signal SECC₁ changes to go high and is fed to the first block. Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signal BS₁₁₁, BS₁₁₂ and BS₁₁₄ and the second control signal SECC₁, with timing in which the block forcedly activating signal BFAT₁ changes to go high, the high-level main-word timing control signal MTC₁ is output.

In a state where all the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₁ and, at the same time, the third control signal THIC₁ used to control timing with which the sub-word activating signal SWAT₁ is output to the first bank is fed as the low-level signal, a high-level signal is output from all the OR gates 53 to 55. Normally, since the block forcedly-activating signal BFAT₁ is fed as a low-level signal and the test clock TCK is not fed, a high-level signal is output from the SR latch 64. Therefore, in this state, the low-level sub-word activating signal SWAT₁ is output from the NAND gate 65. Next, even when any one of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ is fed as the low-level signal, if the third control signal THIC₁ remains at a low level, no changes occur. When the third control signal THIC₁ changes to go high, since any one of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which any one of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ has been fed. This causes the NAND gate 65 to output the high-level sub-word activating signal SWAT₁ which is then fed to the first block. That is, after the activating signal generating circuit 20 ₁ has been selected from 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the high-level block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄, a high-level sub-word activating signal SWAT₁ is output with timing in which the third control signal THIC₁ changes to go high and is fed to the first block. Moreover, at a time of the test, the test clock TCK is first fed and, after the block forcedly-activating signal BFAT₁ has risen to go high at a time of a first rise of the test clock TCK, an output signal from the SR latch 64 changes to go low at a time of a fist fall of the test clock TCK. Therefore, the high-level sub-word activating signal SWAT₁ is output, irrespective of supply of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ and the third control signal THIC₁, with timing in which the test clock TCK first falls.

In a state where all the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₁ and, at the same time, the fourth control signals FORC₁₁ and FORC₂₁ used to control timing in which two kinds of the SA activating signals SAAT₁ and SAAT₂ are output to the first bank are fed as low-level signals, a high-level signal is output from all the OR gates 56 to 61. Therefore, in this state, the low-level SA activating signals SAAT₁₁ and SAAT₂₁ are output from both the NAND gates 66 and 67. Next, even when any one of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ is fed as the low-level signal, if both the fourth control signals FORC₁₁ and FORC₂₁ remain at a low level, no changes occur. When the fourth control signal FORC₁₁ changes to go high, since any one of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which the fourth control signal FORC₁₁ is fed. This causes the NAND gate 66 to output the high-level SA activating signal SATT₁₁, which is then fed to the first block. Moreover, when the fourth control signal FORC₂₁ changes to go high, since any one of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which any one of the block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄ has been fed. This causes the NAND gate 67 to output a high-level SA activating signal SATT₂₁, which is then fed to the first block. That is, after the activating signal generating circuit 20 ₁ has been selected from 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the high-level block selecting signals BS₁₁₁, BS₁₁₂ and BS₁₁₄, the high-level SA activating signals SAAT₁₁ and SAAT₂₁ are sequentially output with timing in which the fourth control signals FORC₁₁ and FORC₂₁ change sequentially to go high, which are then fed to the first block.

The block activating section 16 ₂, as shown in FIG. 10, includes a block selecting signal generating circuit 18 ₂, a row address latch signal generating circuit 19 ₂ and an activating signal generating circuit 20 ₂.

The block selecting signal generating circuit 18 ₂, based on the block activating designation signals ATD₂, ATD₄ and ATD₈ fed from the refresh decoder 15, latch signals LT₁ and LT₂, reversed latch signals /LT₁ and /LT₂, refresh mode signal RM₀₅, bank mode signals BM₁, BM₂ and BM₄ and capacity mode signals CM₂, CM₄ and CM₈ all of which are fed from the control circuit 3, generates any one of a block selecting signal BS₂₁₁ used to activate the second block, if the memory block 1 is made up of one bank, by using the whole blocks belonging to the bank, a block selecting signal BS₂₁₂ used to activate the second block, if the memory block 1 is made up of two banks, by using the whole blocks belonging to the first bank, a block selecting signal BS₂₁₄ used to activate the second block, if the memory block 1 is made up of four banks, by using the whole blocks belonging to the first bank, a block selecting signal BS₂₂₂ used to activate the second block, if the memory block 1 is made up of two banks, by using the whole blocks belonging to the second bank and a block selecting signal BS₂₂₄ used to activate the second block, if the memory block 1 is made up of four banks, by using the whole blocks belonging to the second bank.

FIG. 11 is a schematic block diagram showing one example of configurations of the block selecting signal generating circuit 18 ₂ employed in the memory according to the embodiment. The block selecting signal generating circuit 18 ₂ of the embodiment includes OR gates 68 and 69 each having two inputs, AND gates each having two inputs, OR gate having three inputs, OR gate 79 having four inputs, NAND gates 80 to 84 each having two inputs, transfer gates 85 to 89, latches 90 to 94 and inverters 95 to 99. When the refresh mode signal RM₀₅ which goes high when the system designer sets the number of rows of memory cell arrays to be refreshed at 512 and the capacity mode signal CM₄ which goes high when the system designer sets a storage capacity at 4M bits are fed simultaneously, a high-level signal is output from the AND gate 74. Therefore, if the bank mode signal BM₄ which has gone high because the system designer had set the number of banks at 4, has been fed, a low-level signal is output from the NAND gate 80, which passes through the transfer gate 85 being turned ON and is reversed by the latch 90 to go high and then is again reversed by the inverter 95 to go low and is then output as the low-level block selecting signal BS₂₂₄ used to select the second block, if the memory block 1 is made up of four banks, by using the whole blocks belonging to the second bank. Then, when the high-level latch signal LT₂ and the low-level reversed latch signal /LT₂ used to temporarily latch the block selecting signal BS to be fed to all the blocks belonging to the second bank are fed from the control circuit 3, since the transfer gate 85 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₂₂₄ obtained before being reversed is being latched by the latch 85. Moreover, an aim of temporarily holding the state of the block selecting signal BS₂₂₄ obtained before being reversed in the latch 85 by using the high-level latch signal LT₂ and the low-level reversed latch signal /LT₂ is to prevent the block being now operated from becoming inactivated even when other blocks are activated at a later time compared with the block being now operated. The latches 91 to 94 are mounted because of the same reasons as above.

When either the high-level refresh mode signal RM₀₅ or the block activating designation signal ATD₂ which is produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 1k and when the high-level row address higher-bit signal RAD₁₀ is fed and the capacity mode signal CM₈ which goes high when the system designer sets a storage capacity at 8M bits, are fed simultaneously, a high-level signal is output from the AND gate 75. Therefore, if the high-level bank mode signal BM₄ has been fed, a low-level signal is output from the NAND gate 81, which passes through the transfer gate 87 being turned ON and is reversed by the latch 92 to go high and is again reversed by the inverter 96 to go low and is then output as the low-level block selecting signal BS₂₁₄ used to activate the second block, if the memory block 1 is made up of four banks, by using the whole blocks belonging to the first bank. Then, when the high-level latch signal LT₁ and low-level reversed latch signal /LT₁ used to temporarily latch the block selecting signal BS to be fed to all the blocks belonging to the second bank are fed from the control circuit 3, since the transfer gate 87 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₂₁₄ obtained before being reversed is being latched by the latch 92.

Also, when both the high-level refresh mode signal RM₀₅ and the capacity mode signal CM₈ which goes high when the system designer sets the storage capacity at 2M bits, are fed simultaneously, a high-level signal is output from the AND gate 76. Therefore, if the high-level bank mode signal BM₄ produced because the system designer had set the number of banks at 2, has been fed, a low-level signal is output from the NAND gate 82 and, which passes through the transfer gate 86 being turned ON and is reversed by the latch 91 to go high and then is again reversed by the inverter 97 to go low, which is then output as the low-level block selecting signal BS₂₂₂ used to activate the second block, if the memory block 1 is made up of two banks, by using the whole blocks belonging to the second bank. Then, when the high-level latch signal LT₂ and the low-level reversed latch signal /LT₂ are fed from the control circuit 3, since the transfer gate 86 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₂₁₄ obtained before being reversed is being latched by the latch 91.

When both the block activating designation signal ATD₄ which is generated when the system designer sets the number of rows of memory cell arrays to be refreshed at 2k and when the high-level row address higher-bit signal RAD₁₀ and high-level reversed row address higher-bit signal /RAD₁₁ are fed and the high-level capacity mode signal CM₈ are fed simultaneously to the AND gate 70, a high-level signal is output from the AND gate 70. When both the high-level refresh mode signal RM₀₅ and the high-level capacity mode signal CM₈ are simultaneously fed to the AND gate 71, a high-level signal is output from an AND gate 71. When both the high-level refresh mode signal RM₀₅ and the high-level capacity mode CM₄ are simultaneously fed to the AND gate 72, a high-level signal is output from then AND gate 72. Accordingly, when the block activating designation signal ATD₂ is fed to the OR gate 79, since the high-level signals are output from all the AND gates 70, 71 and 72, a high-level signal is output from the OR gate 79. Therefore, if the high-level bank mode signal BM₂ has been fed, a low-level signal is output from the NAND gate 83, which passes through the transfer gate 88 and is then reversed by the latch 93 to go high and is again reversed by the inverter 98 to go low and is then output as the low-level block selecting signal BS₂₁₂ used to activate the second block, if the memory block 1 is made up of two banks, by using the whole blocks belonging to the first bank. Then, when the high-level latch signal LT₁ and low-level reversed latch signal /LT₁ are fed from the control circuit 3, since the transfer gate 97 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₂₁₂ obtained before being reversed is being latched by the latch 93.

When any one of the block activating designation signals ATD₂ and ATD₄, and ATD₈ produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 4k and when the high-level row address higher-bit signal RAD₁₀, high-level reversed row address higher-bit signal /RAD₁₁ and high-level reversed row address higher-bit signal /RAD₁₂ are fed, is supplied, a high-level signal is output from the OR gate 78. When any one of the high-level capacity mode signals CM₂, CM₄ and CM₈ and the high-level refresh mode signal RM₀₅ are fed, a high-level signal is output from the AND gate 73. Since, in all the above cases, a high-level signal is output from the OR gate 69, if the high-level bank mode signal BM₁ produced because the system designer sets the number of banks at 1, is fed, a low-level signal is output from the NAND gate 84, which passes through the transfer gate 89 and is then reversed by the latch 94 to go high and is again reversed by the inverter 99 to go low, which is then output as the low-level block selecting signal BS₂₁₁ used to activate the second block, if the memory block 1 is made up of one bank, by using all blocks belonging to the bank being operated. Then, when the high-level latch signal LT₁ and the low-level reversed latch signal /LT₁ are fed from the control circuit 3, since the transfer gate 89 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₂₁₁ obtained before being reversed is being latched by the latch 94. Moreover, when the system designer sets the number of rows of memory cell arrays to be refreshed at 512, the high-level refresh mode signal RM₀₅ is fed and even when the system designer sets the number of banks to any value, one of the block selecting signals BS is output. This is because no block activating designation signal ATD is produced, as is understood from FIG. 5.

The row address latch signal generating circuit 19 ₂ shown in FIG. 10, based on the first control signal FIRC₁ and FIRC₂, test mode signal TM and block forcedly-activating signal BFAT₂, block selecting signals BS₂₁₁, BS₂₁₂, BS₂₂₂, BS₂₁₄ and BS₂₂₄ fed from the block selecting signal generating circuit 18 ₂, generates the row address latch signal RLT₂ used to temporarily hold the row address decoded by the row decoder 10 and feeds it to the second block.

FIG. 12 is a schematic block diagram showing one example of configurations of the row address latch signal generating circuit 19 ₂ employed in the memory according to the embodiment. The row address latch signal generating circuit 19 ₂ includes inverters 100 to 102, OR gates 103 to 108 each having two inputs, OR gates each having five inputs and NAND gate 110 having two inputs. In a state where all the block selecting signals BS₂₁₁, BS₂₁₂, BS₂₂₂, BS₂₁₄ and BS₂₂₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₂ and, at the same time, the first control signals FIRC₁ and FIRC₂ used to control timing with which the row address latch signal RLT is output to the first and second banks are fed as low-level signals, since a high-level signal is output from all the OR gates 103 to 107, a high-level signal is output from the AND gate 42. Normally, both the test mode signal TM and block forcedly-activating signal BFAT₂ are fed as low-level signals. Therefore, in this state, the low-level row address latch signal RLT₂ is output from the NAND gate 110. Even when any one of the block selecting signals BS₂₁₁, BS₂₁₂ and BS₂₁₄ is supplied as the low-level signal, if the first control signal FIRC₁ remains at a low level, no changes occur. When the first control signal FIRC₁ changes to go high, since any one of the block selecting signals BS₂₁₁, BS₂₁₂ and BS₂₁₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which any one of the block selecting signals has been fed. This causes the AND gate 109 to output a low-level signal and, therefore, the NAND gate 110 to output the high-level row address latch signal RLT₂, which is then fed to the second block. Similarly, even when either of the block selecting signals BS₂₂₂ or BS₂₂₄ is supplied as the low-level signal, if the first control signal FIRC₂ remains at a low level, no changes occur. When the first control signal FIRC₂ changes to go high, since either of the block selecting signal BS₂₂₂ or BS₂₂₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signal BS₂₂₂ or BS₂₂₄ has been fed. This causes the AND gate 109 to output a low-level signal and, therefore, the NAND gate 110 to output the high-level row address latch signal RLT₂, which is then fed to the second block. That is, after the row address latch signal generating circuit 19 ₂ has been selected out of 8 pieces of the row address latch signal generating circuits 19 ₁ to 19 ₈ by any one of the low-level block selecting signals BS₂₁₁, BS₂₁₂, BS₂₂₂, BS₂₁₄ and BS₂₂₄, the high level row address latch signal RLT₁ is output with timing in which the first control signal FIRC₁ or FIRC₂ changes to go high, and is then fed to the second block. Moreover, since the test mode signal TM changes to go high at a time of the test, irrespective of supply of the block selecting signals BS₂₁₁, BS₂₁₂, BS₂₂₂, BS₂₁₄ and BS₂₂₄ and the first control signals FIRC₁ and FIRC₂, the high-level row address latch signal RLT₂ is output with timing in which the block forcedly-activating signal BFAT₂ changes to go high.

The activating signal generating circuit 20 ₂ shown in FIG. 10, based on the second control signals SECC₁ and SECC₂, third control signals THIC₁ and THIC₂, fourth control signals FORC₁₁, FORC₁₂, FORC₂₁ and FORC₂₂, test mode signal TM, test clock TCK and block forcedly-activating signal BFAT₂ all of which are fed from the control circuit 3, and based on the block selecting signals BS₂₁₁, BS₂₁₂, BS₂₂₂, BS₂₁₄ and BS₂₂₄ fed from the block selecting signal generating circuit 18 ₂, generates the sub-word activating signal SWAT₂ used to activate sub-word lines of the MCA making up the second block contained in the memory block 1, two kinds of the SA activating signals SAAT₁₂ and SAAT₂₂ used to activate the two SAs making up the second block contained in the memory block 1 and the main-word timing control signal MTC₂ used to control timing with which the row decoder 10 outputs the main-word activating signal MWAT and feeds them to the second block.

FIG. 13 a schematic block diagram showing one example of configurations of the activating signal generating circuit 20 ₂ employed in the memory according to the embodiment. The activating signal generating circuit 20 ₂ of the embodiment includes inverters 111 to 119, OR gates 120 to 140 having two inputs, AND gates 141 having four inputs, NAND gate 142 having two inputs, SR latch 143, NAND gate 144 having six inputs and NAND gates 145 to 146 each having five inputs.

Moreover, in a state where all the block selecting signals BS₂₁₁, BS₂₁₂, BS₂₁₄, BS₂₂₂ and BS₂₂₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₂ and, at the same time, all the second control signals SECC₁ and SECC₂ used to control timing with which the main-word timing control signal MTC is output to the first and second banks, are fed as low-level signals, since a high-level signal is output from all the OR gates 120 to 124, a high-level signal is output from the AND gate 141. Normally, all of the test mode signal TM and block forcedly-activating signal BFAT₂ are fed as low-level signals. Therefore, in this state, the low-level main-word timing control signal MTC₂ is output from the NAND gate 142. Even when any one of the block selecting signals BS₂₁₁, BS₂₁₂ and BS₂₁₄ is supplied as the low level signal, if the second control signal SECC₁ remains at a low level, no changes occur. When the second control signal SECC₁ changes to go high, since any one of the block selecting signals BS₂₁₁, BS₂₁₂ and BS₂₁₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which any one of the block selecting signals has been fed. This causes the AND gate 141 to output a low-level signal and, therefore, the NAND gate 142 to output the high-level main-word timing control signal MTC₂, which is then fed to the second block. Similarly, even when either of the low-level block selecting signals BS₂₂₂ or BS₂₂₄ is supplied, if the second control signal SECC₂ remains at a low level, no changes occur. When the second control signal SECC₂ changes to go high, since either the block selecting signal BS₂₂₂ or block selecting signal BS₂₂₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signals has been fed. This causes the AND gate 141 to output a low-level signal and, therefore, the NAND gate 142 to output the high-level main-word timing control signal MTC₂, which is then fed to the second block. That is, after the activating signal generating circuit 20 ₂ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₂₁₁, BS₂₁₂, BS₂₂₂, BS₂₁₄ and BS₂₂₄, the high-level main-word timing control signal MTC₂ is output with timing in which the second control signal SECC₁ or SECC₂ changes to go high, and is then fed to the second block. Moreover, since the test mode signal TM changes to go high at a time of the test, irrespective of supply of the block selecting signals BS₂₁₁, BS₂₁₂, BS₂₂₂, BS₂₁₄ and BS₂₂₄ and the second control signals SECC₁ and SECC₂, the high-level main-word timing control signal MTC₂ is output with timing in which the block forcedly-activating signal BFAT₂ changes to go high.

Moreover, in a state where all the block selecting signals BS₂₁₁, BS₂₁₂, BS₂₂₂, BS₂₁₄ and BS₂₂₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₂ and, at the same time, both the third control signals THIC₁ and THIC₂ used to control timing with which the sub-word activating signal SWAT is output to the first and second banks, are fed as low-level signals, a high-level signal is output from all the OR gates 126 to 130. Normally, the block forcedly-activating signal BFAT₂ are fed as low-level signals and, since the test clock TCK is not supplied, a high-level signal is output from the SR latch 143. Therefore, in this state, the low-level sub-word activating signal SWAT₂ is output from the NAND gate 144. Then, even when any one of the low-level block selecting signals BS₂₁₁, BS₂₁₂ and BS₂₁₄ is supplied, if the third control signal THIC₁ remains at a low level, no changes occur. When the third control signal THIC₁ changes to go high, since any one of the block selecting signals BS₂₂₂, BS₂₁₄ and BS₂₂₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which any one of the block selecting signals has been fed. This causes the NAND gate 144 to output the high-level sub-word activating signal SWAT₂, which is then fed to the second block. Similarly, even when either of the low-level block selecting signals BS₂₂₂ or BS₂₂₄ is supplied, if the third control signal THIC₂ remains at a low level, no changes occur. When the third control signal THIC₂ changes to go high, since either of the block selecting signal BS₂₂₂ or BS₂₂₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signals has been fed. This causes the NAND gate 144 to output the high-level sub-word activating signal SWAT₂, which is then fed to the second block. That is, after the activating signal generating circuit 20 ₂ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₂₁₁, BS₂₁₂, BS₂₂₂, BS₂₁₄ and BS₂₂₄, the high-level sub-word activating signal SWAT₂ is output with timing in which the third control signal THIC₁ or THIC₂ is changed to go high, and is then fed to the second block.

Moreover, at a time of the test, the test clock TCK is first fed and, after the block forcedly-activating signal BFAT₂ has risen to go high at a time of a second rise of the test clock TCK, an output signal from the SR latch 143 changes to go low at a time of a second fall of the test clock TCK. Therefore, a high-level sub-word activating signal SWAT₂ is output, irrespective of supply of the block selecting signals BS₂₁₁, BS₂₁₂, BS₂₂₂, BS₂₁₄ and BS₂₂₄ and the third control signals THIC₁ and THIC₂, with timing in which the test clock TCK first falls.

In a state where all the block selecting signals BS₂₁₁, BS₂₁₂, BS₂₂₂, BS₂₁₄ and BS₂₂₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₂ and, at the same time, the fourth control signals FORC₁₁, FORC₁₂, FORC₂₁ and FORC₂₂, used to control timing with which two kinds of SA activating signals SAAT₁ and SAAT₂ are output to the first and second banks, are fed as low-level signals, a high-level signal is output from all the OR gates 131 to 140. Therefore, in this state, the SA activating signals SAAT₁₂ and SAAT₂₂, both of which are low-level signals, are output from the NAND gates 145 and 146 respectively. Then, even when any one of the low-level block selecting signals BS₂₁₁, BS₂₁₂ and BS₂₁₄ is supplied, if the fourth control signals FORC₁₁ and FORC₂₁ remain at a low level, no changes occur. When the fourth control signal FORC₁₁ changes to go high, since any one of the block selecting signals BS₂₁₁, BS₂₁₂ and BS₂₁₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which any one of the block selecting signals has been fed. This causes the NAND gate 145 to output the high-level SA activating signal SAAT₁₂, which is then fed to the second block. Then, when the fourth control signal FORC₂₁ changes to go high, since any one of the block selecting signals BS₂₁₁, BS₂₁₂ and BS₂₁₄ has changed to be at a low level, a low-level signal is output from the OR gate to which any of the block selecting signals has been fed. This causes the NAND gate 146 to output the high-level SA activating signal SAAT₂₂, which is then fed to the second block. Similarly, even when either of the low-level block selecting signals BS₂₂₂ or BS₂₂₄ is supplied, if the fourth control signals FORC₁₂ and FORC₂₂ remain at a low level, no changes occur. When the fourth control signal FORC₁₂ changes to go high, since either of the block selecting signal BS₂₂₂ or BS₂₂₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signals has been fed. This causes the NAND gate 145 to output the high-level SA activating signal SAAT₁₂, which is then fed to the second block. Then, when the fourth control signal FORC₂₂ changes to go high, since either of the block selecting signals BS₂₂₂ or BS₂₂₄ has changed to at a low level, a low-level signal is output from the OR gate to which either of the block selecting signals has been supplied. This causes the NAND gate 146 to output the high-level SA activating signal SAAT₂₂, which is then fed to the second block. That is, after the activating signal generating circuit 20 ₂ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₂₁₁, BS₂₁₂, BS₂₂₂, BS₂₁₄ and BS₂₂₄, the high-level SA activating signals SAAT₁₂ and SATT₂₂ are sequentially output with timing in which the fourth control signals FORC₁₁, FORC₂₁, FORC₁₂ and FORC₂₂ sequentially change to go high, and is then fed to the second block.

The block activating section 16 ₃, as shown in FIG. 14, includes a block selecting signal generating circuit 18 ₃, a row address latch signal generating circuit 19 ₃ and an activating signal generating circuit 20 ₃.

The block selecting signal generating circuit 18 ₃, based on the block activating designation signals ATD₁, ATD₅ and ATD₉ fed from the refresh decoder 15, latch signals LT₁ to LT₃, reversed latch signals /LT₁ to /LT₃, refresh mode signal RM₀₅, bank mode signals BM₁, BM₂ and BM₄ and capacity mode signals CM₄ and CM₈ all of which are fed from the control circuit 3, generates a block selecting signal BS₃₁₁ used to activate the third block, if the memory block 1 is made up of one bank, by using all blocks belonging to the bank being operated, a block selecting signal BS₃₁₂ used to activate the third block, if the memory block 1 is made up of two banks, by using all blocks belonging to the first bank, a block selecting signal BS₃₂₂ used to activate the third block, if the memory block 1 is made up of two banks, by using all blocks belonging to the second bank, a block selecting signal BS₃₂₄ used to activate the third block, if the memory block 1 is made up of four banks, by using all blocks belonging to the second bank and a block selecting signal BS₃₃₄ used to activate the third block, if the memory block 1 is made up of four banks, by using all blocks belonging to the second bank.

FIG. 15 a schematic block diagram showing one example of configurations of the block selecting signal generating 18 ₃. The block selecting signal generating 18 ₃ of the embodiment includes OR gates 147 to 149 each having two inputs, AND gates 150 to 157 each having two inputs, OR gates 158 and 159 each having four inputs, NAND gates 160 to 164 each having two inputs, transfer gates 165 to 169, latches 170 to 174 and inverters 175 to 179. When both the high-level refresh mode signal RM₀₅ which goes high when the system designer sets the number of rows of memory cell arrays to be refreshed at 512k and the capacity mode signal CM₄ which goes high when the system designer sets a storage capacity at 4M bits, are fed simultaneously, a high-level signal is output from the AND gate 155. Therefore, if the high-level bank mode signal BM₄ which has gone high because the system designer had set the number of banks at four, has been fed, a low-level signal is output from the NAND gate 160, which passes through the transfer gate 165 being turned ON and is reversed by the latch 170 to go high and is again reversed by the inverter 175 to go low and is then output as the low-level block selecting signal BS₃₃₄ used to activate the third block, if the memory block 1 is made up of four banks, by using the whole blocks belonging to the third bank. Then, when the high-level latch signal LT₃ and the low-level reversed latch signal /LT₃ used to temporarily latch the block selecting signal BS to be fed to all the blocks belonging to the third bank are fed from the control circuit 3, the transfer gate 165 is turned OFF and while it is in an OFF state, a state of the block selecting signal BS₃₃₄ obtained before being reversed is being latched by the latch 170. Moreover, an aim of temporarily holding the state of the block selecting signal BS₃₃₄ obtained before being reversed in the latch 170 by using the high-level latch signal LT₃ and the low-level reversed latch signal /LT₃ is to prevent the block being now operated from becoming inactivated even when other blocks are activated at a later time compared with the block being now operated. The latches 171 to 174 are mounted because of the same reasons as above.

When either the high-level refresh mode signal RM₀₅ or the block activating designation signal ATD₁ which is produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 1k and when the high-level reversed row address higher-bit signal /RAD₁₀ is fed and the capacity mode signal CM₈ which goes high when the system designer sets a storage capacity at 8M bits, are fed simultaneously, a high-level signal is output from the AND gate 156. Therefore, if the high-level bank mode signal BM₄ has been fed, a low-level signal is output from the NAND gate 161, which passes through the transfer gate 166 being turned ON and is reversed by the latch 171 to go high and is again reversed by the inverter 176 to go low and is then output as the low-level block selecting signal BS₃₂₄ used to activate the third block, if the memory block 1 is made up of four banks, by using the whole blocks belonging to the second bank. Then, when the high-level latch signal LT₁ and the low-level reversed latch signal /LT₁ used to temporarily latch the block selecting signal BS to be fed to all the blocks belonging to the second bank are fed from the control circuit 3, since the transfer gate 166 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₃₂₄ obtained before being reversed is being latched by the latch 171.

When either the high-level refresh mode signal RM₀₅ or the high-level block activating designation signal ATD₁ and the high-level capacity mode CM₄ are fed simultaneously, a high-level signal is output from the AND gate 157. Therefore, if the high-level bank mode BM₂ which has gone high because the system designer had set the number of banks at 2, has been fed, a low-level signal is output from the NAND gate 162, which passes through the transfer gate 167 and is reversed by the latch 172 to become high and is again reversed by the inverter 177 to become low and is then output as the low-level block selecting signal BS₃₂₂ used to activate the third block, if the memory block 1 is made up of two banks, by using the whole blocks belonging to the second bank. Then, when the high-level latch signal LT₂ and the low-level reversed latch signal /LT₂ are fed from the control circuit 3, since the transfer gate 167 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₃₂₂ obtained before being reversed is being latched by the latch 172.

When both the block activating designation signal ATD₅ which is produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 2k and when the high-level reversed row address higher-bit signals /RAD₁₀ and the high-level row address higher-bit signal RAD₁₁ are fed and the capacity mode signal CM₈ are supplied simultaneously, a high-level signal is output from an AND gate 150. When both the high-level block activating designation signal ATD₁ and the high-level capacity mode signal CM₈ are fed, a high-level signal is output from an AND gate 151. When both the high-level refresh mode signal RM₀₅ and the high-level capacity mode signal CM₈ are fed simultaneously, a high-level signal is output from the AND gate 152. Accordingly, when the block activating designation signal ATD₉ produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 4k and when the high-level reversed row address higher-bit signal /RAD₁₀, high-level row address higher-bit signal RAD₁₁ and high-level reversed row address higher-bit signal /RAD₁₂ are fed, since the high-level signals are output from the all AND gates 150, 151 and 153, a high-level signal is output from the OR gate 158. Therefore, if the high-level bank mode BM₂ produced has been fed, a low-level signal is output from the NAND gate 162, which passes through the transfer gate 168 being turned ON and is reversed by the latch 173 to go high and is again reversed by the inverter 178 to go low and is then output as the low-level block selecting signal BS₃₁₂ used to activate the third block, if the memory block 1 is made up of two banks, by using the whole blocks belonging to the first bank. Then, when the high-level latch signal LT₁ and the low-level reversed latch signal /LT₁ used to temporarily hold the block selecting signal BS to be fed to all the block belonging to the first bank are fed from the control circuit 3, since the transfer gate 168 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₃₁₂ obtained before being reversed is being latched by the latch 173.

Moreover, in all cases where either the block activating designation signal ATD₅ or ATD₉ is fed and where the high-level refresh mode signal RM₀₅ is fed and where either the high-level capacity mode signal CM₄ or CM₈ and the high-level block activating designation signal ATD₁ are simultaneously fed, a high-level signal is output from the OR gate 159. Therefore, if the high-level bank mode BM₁ produced because the system designer sets the number of banks at 1 has been fed to the NAND gate 164, a high-level signal is output from the NAND gate 164, which passes through the transfer gate 169 being turned ON and is reversed by the latch 174 to go high and is again reversed by the inverter 179 to go low and is then output as the low-level block selecting signal BS₃₁₁ used to activate the third block, if the memory block 1 is made up of one bank, by using the whole blocks belonging to the bank being operated. When the high-level latch signal LT₁ and the low-level reversed latch signal /LT₁ are fed, since the transfer gate 169 is turned OFF, while the transfer gate 169 is in an OFF state, a state of the block selecting signal BS₃₁₁ obtained before being reversed is being held by the latch 174. Moreover, when the system designer sets the number of rows of memory cell arrays to be refreshed at 512, the high-level refresh mode signal RM₀₅ is fed and even when the system designer sets the number of banks to any value, one of the block selecting signals BS is output. This is because no block activating designation signal ATD is produced, as is understood from FIG. 5.

The row address latch signal generating circuit 19 ₃ shown in FIG. 14, based on first control signals FIRC₁ to FIRC₃ and test mode signal TM, block forcedly-activating signal BFAT₃ all of which are output from the control circuit 3 and block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄ supplied from the block selecting signal generating circuit 18 ₃, generates the row address latch signal RLT₃ used to temporarily hold row addresses decoded by the row decoder 10 (see FIG. 3) and feeds them to the third block.

FIG. 16 is a schematic block diagram showing one example of configurations of the row address latch signal generating circuit 19 ₃ employed in the memory according to the embodiment The row address latch signal generating circuit 19 ₃ of the embodiment includes inverters 180 to 183, OR gates 184 to 189 each having two inputs, an AND gate 190 and a NAND gate 191 having two inputs.

In a state where all the block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₃ and, at the same time, the first control signals FIRC₁ to FIRC₃ used to control timing with which the row address latch signal RLT is output to the first to third banks, are fed as low-level signals, since a high-level signal is output from all the OR gates 184 to 188, a high-level signal is output from the AND gate 190. Normally, both the test mode signal TM and the block forcedly-activating signal BSAT₃ are fed as the low-level signal. Therefore, in this state, the low-level row address latch signal RLT₃ is output from the NAND gate 191. Next, even when either the low-level block selecting signal BS₃₁₁ or BS₃₁₂ is fed, if the first control signal FIRC₁ remains at a low level, no changes occur. Then, when the first control signal FIRC₁ changes to go high, since either of the block selecting signals BS₃₁₁or BS₃₁₂ has changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signals has been fed. This causes the AND gate 190 to output a low-level signal and, therefore, the NAND gate 191 to output the high-level row address latch signal RLT₃, which is then fed to the third block. Similarly, even when either of the low-level block selecting signals BS₃₂₂ or BS₃₂₄ is supplied as the low-level signal, if the first control signal FIRC₂ remains at a low level, no changes occur. When the first control signal FIRC₂ changes to go high, since either of the block selecting signal BS₃₂₂ or BS₃₂₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signals has been fed. This causes the AND gate 190 to output a low-level signal and, therefore, the NAND gate 191 to output the high-level row address latch signal RLT₃, which is then fed to the third block. Similarly, even when the low-level block selecting signal BS₃₃₄ is fed, if the first control signal FIRC₃ remains at a low level, no changes occur. Then, when the first control signal FIRC₃ goes high, since the block selecting signal BS₃₃₄ has been changed to be at a low level, a low-level signal is output from the OR gate 188. This causes the AND gate 190 to output a low-level signal and, therefore, the NAND gate 191 to output the high-level row address latch signal RLT₃, which is then fed to the third block. That is, after the row address latch signal generating circuit 19 ₃ has been selected out of 8 pieces of the row address latch signal generating circuits 19 ₁ to 19 ₈ by any one of the low-level block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄, the high-level row address latch signal RLT₃ is output with timing in which the first control signals FIRC₁ and FIRC₃ are changed to go high, and is then fed to the third block.

Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄ and the first control signals FIRC₁ to FIRC₃, the high-level row address latch signal RLT₃ is output with timing in which the block forcedly-activating signal BFAT₃ changes to go high.

The activating signal generating circuit 20 ₃ shown in FIG. 14, based on the second control signals SECC₁ to SECC₃, third control signals THIC₁ to THIC₃, fourth control signals FORC₁₁ to FORC₁₃ and FORC₂₁ to FORC₂₃ test mode signal TM, test clock TCK and block forcedly-activating signal BFAT₃ all of which are fed from the control circuit 3 and the block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄ fed from the block selecting signal generating circuit 18 ₃, generates the sub-word activating signal SWAT₃ used to activate sub-word lines of the MCA making up the third block contained in the memory block 1, two kinds of SA activating signals SAAT₁₃ and SAAT₂₃ used to activate two SAs making up the third block contained in the memory block 1 and the main-word timing control signal MTC₃ used to control timing with which the row decoder 10 outputs the main-word activating signal MWAT, and feeds them to the third block.

FIG. 17 is a schematic block diagram showing one example of configurations of the activating signal generating circuit 20 ₃ employed in the memory according to the embodiment. The activating signal generating circuit 20 ₃ includes inverters 192 to 204, OR gates 205 to 225 each having two inputs, AND gate 226 having five inputs, NAND gate 227 having two inputs, SR latch 228, NAND gate 229 having six inputs and NAND gates 230 and 231 each having five inputs.

In a state where all the block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₃ and, at the same time, the second control signals SWCC₁ to SECC₃ used to control timing with which the main-word timing control signal MTC is output to the first to third banks, are fed as low-level signals, since high-level signals are output from all the OR gates 205 to 209, a high-level signal is output from the AND gate 226. Moreover, normally, both the test mode signal TM and the block forcedly-activating signal BFAT₃ are fed as low-level signals. Therefore, in this state, the low-level main-word timing control signal MTC₃ is output from the NAND gate 227. Then, even if either of the low-level block selecting signal BS₃₁₁, or BS₃₁₂ is fed, if the second control signal SECC₁ remains at a low level, no changes occur. When the second control signal SECC₁ changes to go high, since either of the block selecting signal BS₃₁₁ or BS₃₁₂ has changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signal BS₃₁₁ or BS₃₁₂ has been fed. Since this causes the AND gate 226 to output a low-level signal, the high-level main-word timing control signal MTC₃ is output from the NAND gate 227 and is then fed to the third block. Similarly, even when either of the low-level block selecting signal BS₃₂₂ or BS₃₂₄ is fed, if the second control signal SECC₂ remains at a low level, no changes occur. When the second control signal SECC₂ changes to go high, since either of the block selecting signal BS₃₂₂ or BS₃₂₄ has changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signal BS₃₂₂ or BS₃₂₄ has been fed. This causes the AND gate 226 to output a low-level signal and, therefore, the NAND gate 227 to output the high-level main-word timing control signal MTC₃, which is then fed to the third block. Similarly, even when the low-level block selecting signal BS₃₃₄ is fed, if the second control signal SECC₃ remains at a low level, no changes occur. Then, when the second control signal SECC₃ goes high, since the block selecting signal BS₃₃₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which the block selecting signal BS₃₃₄ has been fed. This causes the AND gate 226 to output a low-level signal and, therefore, the NAND gate 227 to output the high-level main-word timing control signal MTC₃, which is then fed to the third block. That is, after the row address latch signal generating circuit 20 ₃ has been selected from 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄, the high-level main-word timing control signal MTC₃ is output with timing in which any one of the second control signals SECC₁, SECC₂ and SECC₃ is changed to go high, and is then fed to the third block. Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄ and the second control signals SECC₁ to SECC₃, with timing in which the block forcedly-activating signal BFAT₃ changes to go high, the high-level main-word timing control signal MTC₃ is output.

In a state where all the block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₃ and, at the same time, the third control signals THIC₁ to THIC₃ used to control timing in which the sub-word activating signal SWAT is output to the first to third banks, are fed as low-level signals, a high-level signal is output from all the OR gates 211 to 215. Moreover, normally, since the block forcedly-activating signal BFAT₃ is fed as the low-level signal and no test clock TCK is fed, a high-level signal is output from the SR latch 228. Therefore, in this state, the low-level sub-word activating signal SWAT₃ is output from the NAND gate 229. Then, even when either of the low-level block selecting signal BS_(311 or BS) ₃₁₂ is fed, if the third control signal THIC₁ remains at a low level, no changes occur. When the third control signal THIC₁ goes high, since either of the block selecting signal BS₃₁₁ or BS₃₁₂ has been changed to be at a low level, a low-level signal is output from the OR gate to which the block selecting signal BS₃₁₁ or BS₃₁₂ has been fed. This causes the NAND gate 229 to output the high-level sub-word activating signal SWAT₃, which is then fed to the third block. Similarly, even when either of the low-level block selecting signal BS₃₂₂ or BS₃₂₄ is fed, if the third control signal THIC₂ remains at a low level, no changes occur. Then, when the third control signal THIC₂ goes high, since either of the block selecting signal BS₃₂₂ or BS₃₂₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signal BS₃₂₂ or BS₃₂₄ has been fed. This causes the NAND gate 229 to output a low-level sub-word activating signal SWAT₃, which is then fed to the third block. Similarly, even when the low-level block selecting signal BS₃₃₄, is supplied, if the third control signal THIC₃ remains at a low level, no changes occur. Then, when the third control signal THIC₃ goes high, since the block selecting signal BS₃₃₄ has been changed to be at a low level, a low-level signal is output from the OR gate 215. This causes the NAND gate 229 to output a high-level sub-word activating signal SWAT₃, which is then fed to the third block. That is, after the activating signal generating circuit 20 ₃ has been selected from 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄, the high-level sub-word activating signal SWAT₃ is output with timing in which any one of the third control signals THIC₁, THIC₂ and THIC₃ is changed to go high, and is then fed to the third block. Moreover, at a time of the test, the test clock TCK is first fed and, after the block forcedly-activating signal BFAT₃ has risen to go high at a time of a third rise of the test clock TCK, an output signal from the SR latch 228 changes to go low at a time of a third fall of the test clock TCK. Therefore, a high-level sub-word activating signal SWAT₃ is output, irrespective of supply of the block selecting signals BS₃₁₁, BS₃₁₂ and BS₃₂₂, BS₃₂₄ and BS₃₃₄ and the third control signals THIC₁ to THIC₃, with timing in which the test clock TCK falls third.

In a state where all the block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₃ and, at the same time, the fourth control signals FORC₁₁ to FORC₁₃ and FORC₂₁ to FORC₂₃ used to control timing in which the two kinds of the SA activating signals SAAT₁ and SAAT₂ are output to the first to third banks, are fed as low-level signals, a high-level signal is output from all the OR gates 216 to 225. Therefore, in this state, low-level SA activating signals SATT₁₃ and SATT₂₃ is output from the NAND gate 230.

Next, even when either of the low-level block selecting signal BS₃₁₁ or BS₃₁₂ is fed, if both the fourth control signals FORC₁₁ and FORC₂₁ remain at a low level, no changes occur. Then, when the fourth control signal FORC₁₁ goes high, since either of the block selecting signal BS₃₁₁ or BS₃₁₂ has been changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signal BS₃₁₁ or BS₃₁₂ has been fed. This causes the NAND gate 230 to output the high-level SA activating signal SAAT₁₃, which is then fed to the third block. Then, when the fourth control signal FORC₂₁ goes high, since either of the block selecting signal BS₃₁₁ or BS₃₁₂ has been changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signal BS₃₁₁ or BS₃₁₂ has been fed. This causes the NAND gate 231 to output the high-level SA activating signal SAAT₂₃, which is then fed to the third block. Similarly, even when either of the low-level block selecting signal BS₃₂₂ or BS₃₂₄ is fed, if both the fourth control signals FORC₁₂ and FORC₂₂ remain at a low level, no changes occur. Then, when the fourth control signal FORC₁₂ goes high, since either of the block selecting signal BS₃₂₂ or BS₃₂₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signal BS₃₂₂ or BS₃₂₄ has been fed. This causes the NAND gate 230 to output the high-level SA activating signal SAAT₁₃, which is then fed to the third block. Then, when the fourth control signal FORC₂₂ goes high, since either of the block selecting signal BS₃₂₂ or BS₃₂₄ has been changed to be at a low level, a low-level signal is output from the OR gate to which either of the block selecting signal BS₃₂₂ or BS₃₂₄ has been fed. This causes the NAND gate 231 to output the high-level SA activating signal SAAT₂₃, which is then fed to the third block.

Similarly, even when the low-level block selecting signal BS₃₃₄ is fed, if both the fourth control signals FORC₁₃ and FORC₂₃ remain at a low level, no changes occur. Then, when the fourth control signal FORC₁₃ first goes high, since the block selecting signal BS₃₃₄ has been changed to be at a low level, a low-level signal is output from the OR gate 220. This causes the NAND gate 230 to output the high-level SA activating signal SAAT₁₃, which is then fed to the third block. Furthermore, when the fourth control signal FORC₂₃ goes high, since the block selecting signal BS₃₃₄ has been changed to be at a low level, a low-level signal is output from the OR gate 225. This causes the NAND gate 231 to output the high-level SA activating signal SAAT₂₃, which is then fed to the third block. That is, after the activating signal generating circuit 20 ₃ has been selected from 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄, the high-level SA activating signals SAAT₁₃ and SAAT₂₃ are sequentially output with timing in which the fourth control signals FORC₁₁, FORC₁₂, FORC₁₃, FORC₂₂ and FORC₂₃ are sequentially changed to go high.

The block activating section 16 ₄, as shown in FIG. 18, includes a block selecting signal generating circuit 18 ₄, a row address latch signal generating circuit 19 ₄ and an activating signal generating circuit 20 ₄.

The block selecting signal generating circuit 18 ₄, based on the block activating designation signals ATD₂, ATD₆ and ATD₁₀ fed from the refresh decoder 15, latch signals LT₁, LT₂ and LT₄, reversed latch signals /LT₁, /LT₂ and /LT₄, refresh mode signal RM₀₅, bank mode signals BM₁, BM₂ and BM₄ and capacity mode signals CM₄ and CM₈ all of which are fed from the control circuit 3, generates any one of a block selecting signal BS₄₁₁ used to activate the fourth block, if the memory block 1 is made up of one bank, by using all blocks belonging to the bank being operated, a block selecting signal BS₄₁₂ used to activate the fourth block, if the memory block 1 is made up of two banks, by using all blocks belonging to the first bank, a block selecting signal BS₄₂₂ used to activate the fourth block, if the memory block 1 is made up of two banks, by using all blocks belonging to the second bank, a block selecting signal BS₄₂₄ used to activate the fourth block, if the memory block 1 is made up of four banks, by using all blocks belonging to the second bank and a block selecting signal BS₄₄₄ used to activate the fourth block, if the memory block 1 is made up of four banks, by using all blocks belonging to the second bank.

FIG. 19 is a schematic block diagram showing one example of configurations of the block selecting signal generating 18 ₄ employed in the memory according to the embodiment. The block selecting signal generating 184 of the embodiment includes OR gates 232 to 243 each having two inputs, AND gates 235 to 242 each having two inputs, OR gate 243 having three inputs, OR gate 244 each having four inputs, NAND gates 245 to 249 each having two inputs, transfer gates 250 to 254, latches 255 to 259 and inverters 260 to 264.

When both the high-level refresh mode signal RM₀₅ which goes high when the system designer sets the number of rows of memory cell arrays to be refreshed at 512k and the capacity mode signal CM₄ which goes high when the system designer sets a storage capacity at 4M bits, are fed simultaneously, a high-level signal is output from the AND gate 240. Therefore, if the high-level bank mode signal BM₄ which has gone high because the system designer had set the number of banks at 4, has been fed, a low-level signal is output from the NAND gate 245, which passes through the transfer gate 250 being turned ON and is reversed by the latch 255 to go high and then is again reversed by the inverter 260 to go low and is then output as the low-level block selecting signal BS₄₄₄ used to activate the fourth block, if the memory block 1 is made up of four banks, by using the whole blocks belonging to the fourth bank. Then, when the high-level latch signal LT₄ and the low-level reversed latch signal /LT₄ used to temporarily latch the block selecting signal BS to be fed to all the blocks belonging to the fourth bank are fed from the control circuit 3, the transfer gate 250 is turned OFF and while it is in an OFF state, a state of the block selecting signal BS₄₄₄ obtained before being reversed is being latched by the latch 255. Moreover, an aim of temporarily holding the state of the block selecting signal BS₄₄₄ obtained before being reversed in the latch 255 by using the high-level latch signal LT₄ and the low-level reversed latch signal /LT₄ is to prevent the block being now operated from becoming inactivated even when other blocks are activated at a later time compared with the block being now operated. The latches 256 to 257 are mounted because of the same reasons as above.

When either the high-level refresh mode signal RM₀₅ or the block activating designation signal ATD₂ which is produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 1k and when the high-level row address higher-bit signal RAD₁₀ is fed and the capacity mode signal CM₈ which goes high when the system designer sets a storage capacity at 8M bits, are fed simultaneously, a high-level signal is output from the AND gate 241. Therefore, if the high-level bank mode signal BM₄ has been fed, a low-level signal is output from the NAND gate 246, which passes through the transfer gate 251 being turned ON and is reversed by the latch 256 to go high and is again reversed by the inverter 261 to go low and is then output as a low-level block selecting signal BS₄₂₄ used to activate the fourth block, if the memory block 1 is made up of four banks, by using the whole blocks belonging to the second bank. Then, when the high-level latch signal LT₂ and the low-level reversed latch signal /LT₂ used to temporarily latch the block selecting signal BS to be fed to all the blocks belonging to the second bank are fed from the control circuit 3, since the transfer gate 251 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₃₂₄ obtained before being reversed is being latched by the latch 256.

When either the high-level refresh mode signal RM₀₅ or the high-level block activating designation signal ATD₂ and the high-level capacity mode CM₄ are fed simultaneously, a high-level signal is output from the AND gate 242. Therefore, if the high-level bank mode BM₂ which has gone high because the system designer had set the number of banks at 2, has been fed, a low-level signal is output from the NAND gate 247, which passes through the transfer gate 252 and is reversed by the latch 257 to go high and is again reversed by the inverter 262 to go low and is then output as the low-level block selecting signal BS₄₂₂ used to activate the fourth block, if the memory block 1 is made up of two banks, by using the whole blocks belonging to the second bank. Then, when the high-level latch signal LT₂ and the low-level reversed latch signal /LT₂ are fed from the control circuit 3, since the transfer gate 252 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₄₂₂ obtained before being reversed is being latched by the latch 257.

When both the block activating designation signal ATD₆ which is produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 2k and when the high-level row address higher-bit signals RAD₁₀ and the high-level row address higher-bit signal RAD₁₁ are fed and the capacity mode signal CM₈ are fed simultaneously, a high-level signal is output from the AND gate 235. Moreover, when both the high-level block activating designation signal ATD₂ and the high-level capacity mode signal CM₈ are fed, a high-level signal is output from the AND gate 236. When both the high-level refresh mode signal RM₀₅ and the high-level capacity mode signal CM₈ are fed simultaneously, a high-level signal is output from the AND gate 237. Since a high-level signal is output from the OR gate 243 in any case, if the high-level bank mode signal BM₂ has been fed, a low-level signal is output from the NAND gate 248, which passes through the transfer gate 253 being turned ON and is reversed by the latch 258 to become high and then again reversed by the inverter 263 to become low and is output as the low-level block selecting signal BS₄₁₂ used to activate the fourth block, if the memory block 1 is made up of two banks, by using the whole blocks belonging to the first bank. Then, when the high-level latch signal LT₁ and the low-level reversed latch signal /LT₁ used to temporarily hold the block selecting signal BS to be fed to all the block belonging to the first bank are fed from the control circuit 3, since the transfer gate 253 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₄₁₂ obtained before being reversed is being latched by the latch 258.

Moreover, in all cases where either the block activating designation signal ATD₆ or the block activating designation signal ATD₁₀ produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 4 k and when the high-level row address higher-bit signal RAD₁₀, high-level row address higher-bit signal RAD₁₁ and high-level reversed row address higher-bit signal /RAD₁₂ and where either the high-level capacity mode signal CM₄ or CM₃ and the high-level refresh mode signal RM₀₅ are fed simultaneously and where either the high-level capacity mode signal CM₄ or CM₈ and the high-level block activating designation signal ATD₂ are fed simultaneously, a high-level signal is output from the OR gate 244. Therefore, if the high-level bank mode BM₁ which has gone high because the system designer had set the number of banks at one, has been fed to the NAND gate 249, a low-level signal is output from the NAND gate 249, which passes through the transfer gate 169 being turned ON and is reversed by the latch 259 to go high and is again reversed by the inverter 264 to go low and is then output as the low-level block selecting signal BS₄₁₁ used to activate the fourth block, if the memory block 1 is made up of one bank, by using the whole blocks belonging to the bank being operated. When the high-level latch signal LT₁ and the low-level reversed latch signal /LT₁ are fed from the control circuit 3, since the transfer gate 254 is turned OFF, while the transfer gate 254 is in an OFF state, a state of the block selecting signal BS₄₁₁ obtained before being reversed is being held by the latch 259. Moreover, when the system designer sets the number of rows of memory cell arrays to be refreshed at 512, the high-level refresh mode signal RM₀₅ is fed and even when the system designer sets the number of banks to any value, one of the block selecting signals BS is output. This is because no block activating designation signal ATD is produced, as is understood from FIG. 5.

Next, the row address latch signal generating circuit 19 ₄ shown in FIG. 18, based on first control signals FIRC₁, FIRC₂ and FIRC₄ and test mode signal TM, block forcedly-activating signal BFAT₃ all of which are output from the control circuit 3 and block selecting signals BS₄₁₁, BS₄₁₂, BS₄₂₂, BS₄₂₄ and BS₄₄₄ supplied from the block selecting signal generating circuit 18 ₄, generates the row address latch signal RLT₄ used to temporarily hold row addresses decoded by the row decoder 10 (see FIG. 3) and feeds them to the fourth block.

FIG. 20 is a schematic block diagram showing one example of configurations of another row address latch signal generating circuit 19 ₄. In FIG. 20, same reference numbers are assigned to corresponding parts in FIG. 16 and their descriptions are omitted accordingly. In the row address latch signal generating circuit 19 ₄ shown in FIG. 20, instead of the block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄, first control signal FIRC₃ and block forcedly-activating signal BFAT₃ shown in FIG. 16, the block selecting signals BS₄₁₁, BS₄₁₂, BS₄₂₂, BS₄₂₄ and BS₄₄₄ are newly input from the block selecting signal generating circuit 18 ₄ and, at the same time, a first control signal FIRC₄ and block forcedly-activating signal BFAT₄ are newly input from the control circuit 3 and, instead of the row address latch signal RLT₃, the row address latch signal RLT₄ is newly output. That is, configurations of the row address latch signal generating circuit 19 ₄ are the same as those of the row address latch signal generating circuit 19 ₃ except for signals input and output thereto or therefrom. Therefore, after the row address latch signal generating circuit 19 ₄ has been selected out of 8 pieces of the row address latch signal generating circuits 19 ₁ to 19 ₈ by any one of the low-level block selecting signals BS₄₁₁, BS₄₁₂, BS₄₂₂, BS₄₂₄ and BS₄₄₄, the high-level row address latch signal RLT₄ is output with timing in which the first control signals FIRC₁, FIRC₄ and FIRC₄ are changed to go high, and is then fed to the fourth block.

Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₄₁₁, BS₄₁₂, BS₄₂₂, BS₄₂₄ and BS₄₄₄ and the first control signals FIRC₁, FIRC₂ and FIRC₄, the high-level row address latch signal RLT₄ is output with timing in which the block forcedly-activating signal BFAT₄ changes to go high.

The activating signal generating circuit 20 ₄, based on the second control signals SECC₁, SECC₂ and SECC₄, third control signals THIC₁, THIC₂ and THIC₄, fourth control signals FORC₁₁, FORC₁₂, FORC₁₄, FORC₂₁, FORC₂₂ and FORC₂₄, test mode signal TM, test clock TCK and block forcedly-activating signal BFAT₄ all of which are fed from the control circuit 3 and the block selecting signals BS₄₁₁, BS₄₁₂, BS₄₂₂, BS₄₂₄ and BS₄₄₄ fed from the block selecting signal generating circuit 18 ₄, generates the sub-word activating signal SWAT₄ used to activate sub-word lines of the MCA making up the fourth block contained in the memory block 1, two kinds of SA activating signals SAAT₁₄ and SAAT₂₄ used to activate two SAs making up the fourth block contained in the memory block 1 and the main-word timing control signal MTC₄ used to control timing with which the row decoder 10 outputs the main-word activating signal MWAT, and feeds them to the third block.

FIG. 21 is a schematic block diagram showing one example of configurations of the activating signal generating circuit 20 ₄. In FIG. 21, same reference numbers are assigned to corresponding parts in FIG. 17 and their descriptions are omitted accordingly. In the activating signal generating circuit 20 ₄ shown in FIG. 21, instead of the block selecting signals BS₃₁₁, BS₃₁₂, BS₃₂₂, BS₃₂₄ and BS₃₃₄, second control signal FIRC₃, third control signal THIC₃, fourth control signals FORC₁₃ and FORC₂₃ and block forcedly-activating signal BFAT₃ shown in FIG. 17, the block selecting signals BS₄₁₁, BS₄₁₂, BS₄₂₂, BS₄₂₄ and BS₄₄₄ are newly input from the block selecting signal generating circuit 18 ₄ and, at the same time, the second control signal SECC₄, third control signal THIC₄, fourth control signals FORC₁₄ and FORC₂₄ and block forcedly-activating signal BFAT₄ are newly input from the control circuit 3 and, instead of the sub-word activating signal SWAT₃, SA activating signals SAAT₁₃ and SAAT₂₃ and the main-word timing control signal MTC₃, the sub-word activating signal SWAT₄, SA activating signals SAAT₁₄ and SAAT₂₄ and main-word timing control signal MTC₄ are newly output. That is, configurations of the row address latch signal generating circuit 20 ₄ are the same as those of the row address latch signal generating circuit 20 ₃ except for signals input and output thereto or therefrom.

Therefore, after the row address latch signal generating circuit 20 ₄ has been selected out of 8 pieces of the row address latch signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₄₁₁, BS₄₁₂, BS₄₂₂, BS₄₂₄ and BS₄₄₄, the high-level main-word timing control signal MTC₄ is output with timing in which any one of the second control signals SECC₁, SECC₂ and SECC₄ are changed to go high, and is then fed to the fourth block.

Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₄₁₁, BS₄₁₂, BS₄₂₂, BS₄₂₄ and BS₄₄₄ and the second control signals SECC₁, SECC₂ and SECC₄, the high-level main-word timing control signal MTC₄ is output with timing in which the block forcedly-activating signal BFAT₄ changes to go high.

After the activating signal generating circuit 20 ₄ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₄₁₁, BS₄₁₂, BS₄₂₂, BS₄₂₄ and BS₄₄₄, the high-level sub-word activating signal SWAT₄ is output with timing in which any one of the third control signals THIC₁, THIC₂ and THIC₄ is changed to go high, and is then fed to the fourth block.

Moreover, at a time of the test, the test clock TCK is first fed and, after the block forcedly-activating signal BFAT₄ has risen to go high at a time of a fourth rise of the test clock TCK, an output signal from the SR latch 228 changes to go low at a time of a fourth fall of the test clock TCK. Therefore, a high-level sub-word activating signal SWAT₄ is output, irrespective of supply of the block selecting signal BS₄₁₁, BS₄₁₂, BS₄₂₄ and BS₄₄₄ and the third control signals THIC₁, THIC₂ and THIC₄, with timing in which the test clock TCK falls fourth.

Moreover, after the activating signal generating circuit 20 ₄ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₄₁₁, BS₄₁₂, BS₄₂₂, BS₄₂₄ and BS₄₄₄, the high-level SA activating signals SAAT₁₄ and SAAT₂₄ are sequentially output with timing in which two kinds of the fourth control signals FORC₁₁ and FORC₂₁, the fourth control signals FORC₁₂, FORC₂₂, FORC₁₄ and FORC₂₄ are sequentially changed to go high.

The block activating section 16 ₅, as shown in FIG. 22, includes a block selecting signal generating circuit 18 ₅, a row address latch signal generating circuit 19 ₅ and an activating signal generating circuit 20 ₅.

The block selecting signal generating circuit 18 ₅, based on the block activating designation signals ATD₁, ATD₃ and ATD₇ fed from the refresh decoder 15, latch signals LT₁ to LT₃, reversed latch signals /LT₁ to /LT₃, refresh mode signal RM₀₅, bank mode signals BM₁, BM₂ and BM₄ and capacity mode signal CM₈ all of which are fed from the control circuit 3, generates any one of a block selecting signal BS₅₁₁ used to activate the fifth block, if the memory block 1 is made up of one bank, by using all blocks belonging to the bank being operated, a block selecting signal BS₅₂₂ used to activate the fifth block, if the memory block 1 is made up of two banks, by using all blocks belonging to the second bank and a block selecting signal BS₅₄₄ used to activate the fifth block, if the memory block 1 is made up of four banks, by using all blocks belonging to the third bank.

FIG. 23 is a schematic block diagram showing one example of configurations of the block selecting signal generating 18 ₅ employed in the memory according to the embodiment. The block selecting signal generating 18 ₅ of the embodiment includes NOR gates 265 to 267 each having two inputs, NOR gate 268 having three inputs, NAND gates 269 to 273 each having two inputs, NAND gate 274 having three input, transfer gates 275 to 277, latches 278 to 280 and inverters 281 to 283.

When either the high-level refresh mode signal RM₀₅ which goes high when the system designer sets the number of rows of memory cell arrays to be refreshed at 512k or the block activating designation signal ATD₁ produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 1k and when the high-level reversed row address higher-bit signal /RAD₁₀ is fed, and when the high-level capacity mode signal CM₄ which goes high when the system designer sets the storage capacity at 8M bits, if the bank mode signal BM₄ which has gone high because the system designer sets the number of banks at 4 has been fed, a low-level signal is output from the NAND gate 271, which passes through the transfer gate 275 being turned ON and is reversed by the latch 278 to go high and then is again reversed by the inverter 281 to go low and is then output as the low-level block selecting signal BS₅₄₄ used to activate the fifth block, if the memory block 1 is made up of four banks, by using the whole blocks belonging to the third bank. Then, when the high-level latch signal LT₃ and the low-level reversed latch signal /LT₃ used to temporarily latch the block selecting signal BS to be fed to all the blocks belonging to the third bank are fed from the control circuit 3, since the transfer gate 275 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₅₄₄ obtained before being reversed is being latched by the latch 278. Moreover, an aim of temporarily holding the state of the block selecting signal BS₅₄₄ obtained before being reversed in the latch 278 by using the high-level latch signal LT₃ and the low-level reversed latch signal /LT₃ is to prevent the block being now operated from becoming inactivated even when other blocks are activated at a later time compared with the block being now operated. The latches 279 to 280 are mounted because of the same reasons as above.

When any one of the high-level refresh mode signal RM₀₅, the high-level block activating designation signal ATD₁ and the block activating designation signal ATD₃ produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 2k and when the high-level reversed row address higher-bit signal /RAD₁₀ and the high-level reversed row address higher-bit signal /RAD₁₁ are supplied, is fed and, at the same time, the high-level capacity mode signal CM₈ is fed, if the high-level bank mode signal BM₄ which has gone high because the system designer sets the number of banks at 2 has been fed, a low-level signal is output from the NAND gate 272, which passes through the transfer gate 276 being turned ON and is reversed by the latch 279 to go high and then is again reversed by the inverter 282 to go low and is then output as the low-level block selecting signal BS₅₂₂ used to activate the fifth block, if the memory block 1 is made up of two banks, by using the whole blocks belonging to the second bank. Then, when the high-level latch signal LT₂ and the low-level reversed latch signal /LT₂ used to temporarily latch the block selecting signal BS to be fed to all the blocks belonging to the second bank are fed from the control circuit 3, since the transfer gate 276 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₅₂₂ obtained before being reversed is being latched by the latch 279.

When either the high-level refresh mode signal RM₀₅ or the high-level block activating designation signal ATD₁ is fed and either the high-level block activating designation signal ATD₃ or the block activating designation signal ATD₇ produced when the system designer sets the number of rows of memory cell arrays to be refreshed at 4k and when the high-level reversed row address higher-bit signal /RAD₁₀, the high-level reversed row address higher-bit signal /RAD₁₁ and the high-level reversed row address higher-bit signal /RAD₁₂ are supplied, is fed and, at the same time, the high-level capacity mode signal CM₈ is fed, if the high-level bank mode signal BM₄ which has gone high because the system designer had set the number of banks at 2 has been fed, a low-level signal is output from the NAND gate 273, which passes through the transfer gate 277 being turned ON and is reversed by the latch 280 to go high and then is again reversed by the inverter 283 to go low and is then output as the low-level block selecting signal BS₅₁₁ used to activate the fifth block, if the memory block 1 is made up of four banks, by using the whole blocks belonging to the third bank. Then, when the high-level latch signal LT₁ and the low-level reversed latch signal /LT₁ used to temporarily latch the block selecting signal BS to be fed to all the blocks belonging to the first bank are fed from the control circuit 3, since the transfer gate 277 is turned OFF, while it is in an OFF state, a state of the block selecting signal BS₅₁₁ obtained before being reversed is being latched by the latch 280. Moreover, when the system designer sets the number of rows of memory cell arrays to be refreshed at 512, the high-level refresh mode signal RM₀₅ is fed and even when the system designer sets the number of banks to any value, one of the block selecting signals BS is output. This is because no block activating designation signal ATD is produced, as is understood from FIG. 5.

Next, the row address latch signal generating circuit 19 ₅ shown in FIG. 22, based on first control signals FIRC₁ to FIRC₃, test mode signal TM, block forcedly-activating signal BFAT₅ and capacity mode signal CM₈ all of which are output from the control circuit 3 and block selecting signals BS₅₁₁, BS₅₂₂, BS₅₄₄ supplied from the block selecting signal generating circuit 18 ₅, generates the row address latch signal RLT₅ used to temporarily hold row addresses decoded by the row decoder 10 (see FIG. 3) and feeds them to the fifth block.

FIG. 24 is a schematic block diagram showing one example of configurations of another row address latch signal generating circuit 19 ₅ employed in the memory according to the embodiment. The row address latch signal generating circuit 19 ₅ includes inverters 285 to 289, OR gates 290 to 292 each having two inputs, NAND gates 293 to 294 each having three inputs and NAND gate 295 having two inputs.

In a state where all the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₅ and, at the same time, the first control signals FIRC₁ to FIRC₃ used to control timing with which the row address latch signal RLT is output to the first to third banks are fed as low level signals, since a high-level signal is output from all the OR gates 290 to 292, a low-level signal is output from the NAND gate 293. Normally, the test mode TM and the block forcedly-activating signal BFAT₅ are fed as low-level signals. Therefore, when the capacity mode signal CM₈ which goes high when the system designer sets the storage capacity at 8M bits is fed, in this state, the low-level row address latch signal RLT₅ is output from the NAND gate 295. Next, even when the block selecting signals BS₅₁₁ is fed as the low-level signal, if the first control signal FIRC₁ remains at a low level, no changes occur. Then, when the first control signal FIRC₁ changes to go high, since the block selecting signals BS₅₁₁ has been changed to go low, a low-level signal is output from the OR gate 290. Since this causes the NAND gate 293 to output a low-level signal, the high-level row address latch signal RLT₅ is output from the NAND gate 295 and is then fed to the fifth block. Similarly, even if the low-level block selecting signal BS₅₂₂ is fed, if the first control signal FIRC₂ remains at a low level, no changes occur. Then, the first control signal FIRC₂ changes to go high, since the block selecting signal BS₅₂₂ has changed to go low, a low-level signal is output from the OR gate 291. Since this causes the NAND gate 293 to output a high-level signal, the high-level row address latch signal RLT₅ is output from the NAND gate 295, which is then fed to the fifth block. Similarly, even when the low-level block selecting signal BS₅₄₄ is fed, if the first control signal FIRC₃ remains at a low level, no changes occur. When the first control signal FIRC₃ changes to go high, since the block selecting signal BS₅₄₄ has changed to be at a low level, a low-level signal is output from the OR gate 292. Since this causes the NAND gate 293 to output a high-level signal, the high-level row address latch signal RLT₅ is output from the NAND gate 295, which is then fed to the fifth block. That is, after the row address latch signal generating circuit 19 ₅ has been selected out of 8 pieces of the row address latch signal generating circuits 19 ₁ to 19 ₈ by any one of the low-level block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄, the high-level row address latch signal RLT₅ is output with timing in which the first control signals FIRC₁ to FIRC₃ changes to go high, and is then fed to the fifth block. Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄ and the first control signal FIRC₁ to FIRC₃, with timing in which the block forcedly-activating signal BFAT₅ changes to go high, the high-level row address latch signal RLT₅ is output.

The activating signal generating circuit 20 ₅ shown in FIG. 22, based on the second control signals SECC₁ to SECC₃, third control signals THIC₁ to THIC₃, fourth control signals FORC₁₁ to FORC₁₃ and FORC₂₁ to FORC₂₃, test mode signal TM, test clock TCK, block forcedly-activating signal BFAT₅ and capacity mode signal CM₈ all of which are fed from the control circuit 3 and the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄ fed from the block selecting signal generating circuit 18 ₅, generates the sub-word activating signal SWAT₅ used to activate sub-word lines of the MCA making up the fifth block contained in the memory block 1, two kinds of SA activating signals SAAT₁₅ and SAAT₂₅ used to activate two SAs making up the fifth block contained in the memory block 1 and the main-word timing control signal MTC₅ used to control timing with which the row decoder 10 outputs the main-word activating signal MWAT, and feeds them to the fifth block.

FIG. 25 shows one example of configurations of the activating signal generating circuit 20 ₅. The activating signal generating circuit 20 ₅ of the embodiment includes inverters 296 to 309, OR gates 310 to 321 each having two inputs, NAND gates 322 to 326 each having three inputs, NAND gates 327 to 329 each having two inputs, an SR latch 330, AND gates 331 and 332 each having two inputs.

In a state where all the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄ are fed as high-level signals from the block selecting signal generating circuit 18, and, at the same time, the second control signals SECC₁ to SECC₃ used to control timing with which the main-word timing control signal MTC is output to the first to third banks are fed as low level signals, since a high-level signal is output from all the OR gates 310 to 312, a low-level signal is output from the NAND gate 322. Normally, the test mode TM and the block forcedly-activating signal BFAT₅ are fed as low-level signals. Therefore, when the high-level capacity mode signal CM₈ is fed, in this state, the low-level main-word timing control signal MTC₅ is output from the NAND gate 327. Next, even when the block selecting signals BS₅₁₁ is fed as the low-level signal, if the second control signal SECC₁ remains at a low level, no changes occur. Then, when the second control signal SECC₁ changes to go high, since the block selecting signals BS₅₁₁ has been changed to go low, a low-level signal is output from the OR gate 310. Since this causes the NAND gate 322 to output a high-level signal, the high-level main-word timing control signal MTC₅ is output from the NAND gate 327 and is then fed to the fifth block. Similarly, even if the low-level block selecting signal BS₅₂₂ is fed, if the second control signal SECC₁ remains at a low level, no changes occur. Then, the second control signal SECC₂ changes to go high, since the block selecting signal BS₅₂₂ has changed to go low, a low-level signal is output from the OR gate 311. Since this causes the NAND gate 322 to output a high-level signal, the high-level main-word timing control signal MTC₅ is output from the NAND gate 327, which is then fed to the fifth block. Similarly, even when the low-level block selecting signal BS₅₄₄ is fed, if the second control signal SECC₃ remains at a low level, no changes occur. Then, the second control signal SECC₃ changes to go high, since the block selecting signal BS₅₄₄ has changed to go low, a low-level signal is output from the OR gate 312. Since this causes the NAND gate 322 to output a high-level signal, the high-level main-word timing control signal MTC₅ is output from the NAND gate 327, which is then fed to the fifth block. That is, after the activating signal generating circuit 20 ₅ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄, the high-level main-word timing control signal MTC₅ is output with timing in which any one of the second control signals SECC₁, SECC₂ and SECC₃ changes to go high, and is then fed to the fifth block. Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄ and the second control signal SECC₁ to SECC₃, with timing in which the block forcedly-activating signal BFAT₅ changes to go high, the high-level main-word timing control signal MTC₅ is output.

In a state where all the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₅ and, at the same time, the third control signals THIC₁ to THIC₃ used to control timing with which the sub-word activating signal SWAT is output to the first to third banks are fed as low level signals, a high-level signal is output from all the OR gates 313 to 315. Normally, since the block forcedly-activating signal BFAT₅ is fed as the low-level signal and the test clock TCK is not fed, a high-level signal is output from the SR latch 330. Therefore, when the high-level capacity mode signal CM₈ is fed, in this state, the low-level sub-word activating signal SWAT₅ is output from the NAND gate 329. Next, even when the low-level block selecting signals BS₅₁₁ is fed, if the third control signal THIC₁ remains at a low level, no changes occur. Then, when the third control signal THIC₁ changes to go high, since the block selecting signals BS₅₁₁ has been changed to be at a low level, a low-level signal is output from the OR gate 313. Since this causes the NAND gate 324 to output a high-level signal, the high-level sub-word activating signal SWAT₅ is output from the NAND gate 329 and is fed to the fifth block. Similarly, even when the low-level block selecting signal BS₅₂₂ is fed, if the third control signal THIC₂ remains at a low level, no changes occur. Then, the third control signal THIC₂ changes to go high, since the block selecting signal BS₅₂₂ has changed to go low, a low-level signal is output from the OR gate 314. Since this causes the NAND gate 324 to output a high-level signal, the high-level sub-word activating signal SWAT₅ is output from the NAND gate 329, which is then fed to the fifth block. Similarly, even when the low-level block selecting signal BS₅₄₄ is fed, if the third control signal THIC₃ remains at a low level, no changes occur. Then, when the third control signal THIC₃ changes to go high, since the block selecting signal BS₅₄₄ has changed to go low, a low-level signal is output from the OR gate 315. Since this causes the NAND gate 324 to output a high-level signal, the high-level sub-word activating signal SWAT₅ is output from the NAND gate 329, which is then fed to the fifth block. That is, after the activating signal generating circuit 20 ₅ has been selected from 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the high-level block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄, the high-level sub-word activating signal SWAT₅ is output with timing in which any one of the third control signal THIC₁, THIC₂ and THIC₃ changes to go high and is fed to the first block. Moreover, at a time of the test, the test clock TCK is first fed and, after the block forcedly-activating signal BFAT₅ has risen to go high at a time of a fifth rise of the test clock TCK, an output signal from the SR latch 330 changes to go low at a time of a fifth fall of the test clock TCK. Therefore, the high-level sub-word activating signal SWAT₅ is output, irrespective of supply of the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄ and the third control signal THIC₁ to THIC₃ with timing in which the test clock TCK falls fifth.

In a state where all the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄ are fed as high-level signals from the block selecting signal generating circuit 18 ₅ and, at the same time, two kinds of the fourth control signals FORC₁₁ to FORC₁₃ and FORC₂₁ to FORC₂₃ used to control timing with which two kinds of the SA activating signals SAAT₁ and SAAT₂ are output to the first to third banks are fed as low level signals, a high-level signal is output from all the OR gates 316 to 321. Therefore, if the high-level capacity mode signal CM₈ is fed, in this state, the low-level SA activating signal SAAT₁₅ and the low-level SA activating signal SAAT₂₅ are output from the AND gates 331 and 332 respectively.

Next, even when the low-level block selecting signals BS₅₁₁ is fed, if the fourth control signals FORC₁₁ and FORC₂₁ remain at a low level, no changes occur. Then, when the fourth control signal FORC₁₁ changes to go high, since the block selecting signals BS₅₁₁ has been changed to be at a low level, a low-level signal is output from the OR gate 316. Since this causes the NAND gate 325 to output a high-level signal, the high-level SA activating signal SAAT₁₅ is output from the NAND gate 331, which is then fed to the fifth block. Then, when the fourth control signal FORC₂₁ changes to go high, since the block selecting signal BS₅₁₁ has changed to go low, a low-level signal is output from the OR gate 319. Since this causes the NAND gate 326 to output a high-level signal, the high-level SA activating signal SAAT₂₅ is output from the NAND gate 332, which is then fed to the fifth block. Similarly, even when the low-level block selecting signal BS₅₂₂ is fed, if the fourth control signals FORC₁₂ and FORC₂₂ remain at a low level, no changes occur. Then, when the fourth control signal FORC₁₂ changes to go high, since the block selecting signals BS₅₂₂ has been changed to be at a low level, a low-level signal is output from the OR gate 317. Since this causes the NAND gate 325 to output a high-level signal, the high-level SA activating signal SAAT₁₅ is output from the NAND gate 331, which is then fed to the fifth block. Then, when the fourth control signal FORC₂₂ changes to go high, since the block selecting signals BS₅₂₂ has been changed to be at a low level, a low-level signal is output from the OR gate 320. Since this causes the NAND gate 326 to output a high-level signal, the high-level SA activating signal SAAT₂₅ is output from the NAND gate 332, which is then fed to the fifth block. Similarly, even when the low-level block selecting signals BS₅₄₄ is fed, if the fourth control signals FORC₁₃ and FORC₂₃ remain at a low level, no changes occur. Then, when the fourth control signal FORC₁₃ changes to go high, since the block selecting signals BS₅₄₄ has been changed to be at a low level, a low-level signal is output from the OR gate 318. Since this causes the NAND gate 325 to output a high-level signal, the high-level SA activating signal SAAT₁₅ is output from the NAND gate 331, which is then fed to the fifth block. Then, when the fourth control signal FORC₂₃ changes to go high, since the block selecting signal BS₅₄₄ has changed to go low, a low-level signal is output from the OR gate 321. Since this causes the NAND gate 326 to output a high-level signal, the high-level SA activating signal SAAT₂₅ is output from the NAND gate 332, which is then fed to the fifth block. That is, after the activating signal generating circuit 20 ₅ has been selected from 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄, high-level SA activating signals SAAT₁₅ and SAAT₂₅ are sequentially output with timing in which the fourth control signals FORC₁₁, FORC₂₂, FORC₁₂ and FORC₂₂ sequentially change to go high.

The block activating section 16 ₆, as shown in FIG. 26, includes a block selecting signal generating circuit 18 ₆, a row address latch signal generating circuit 19 ₆ and an activating signal generating circuit 20 ₆.

The block selecting signal generating circuit 18 ₆, based on the block activating designation signals ATD₂, ATD₄ and ATD₁₂ fed from the refresh decoder 15, latch signals LT₁ to LT₃, reversed latch signals /LT₁ to /LT₃, refresh mode signal RM₀₅, bank mode signals BM₁, BM₂ and BM₄ and capacity mode signal CM₈ all of which are fed from the control circuit 3, generates any one of a block selecting signal BS₆₁₁ used to activate the sixth block, if the memory block 1 is made up of one bank, by using all blocks belonging to the bank being operated, a block selecting signal BS₆₂₂ used to activate the sixth block, if the memory block 1 is made up of two banks, by using all blocks belonging to the second bank and a block selecting signal BS₆₄₄ used to activate the fifth block, if the memory block 1 is made up of four banks, by using all blocks belonging to the third bank.

FIG. 27 is a schematic block diagram showing one example of configurations of the block selecting signal generating 18 ₆ employed in the memory according to the embodiment. In FIG. 27, same reference numbers are assigned to corresponding parts in FIG. 23 and their descriptions are omitted accordingly. In the block selecting signal generating circuit 18 ₆ shown in FIG. 27, instead of the block activating designation signals ATD₁, ATD₃ and ATD₇ shown in FIG. 23, the block activating designation signals ATD₂, ATD₄ and ATD₁₂ are newly input and, instead of the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄, block selecting signals BS₆₁₁, BS₆₂₂ and BS₆₄₄ are newly output. That is, configurations of the block selecting signal generating circuit 18 ₆ are the same as those of the block selecting signal generating circuit 18 ₅ except for signals input and output thereto or therefrom. Next, the row address latch signal generating circuit 19 ₆ shown in FIG. 26, based on the first control signals FIRC₁ to FIRC₃, test mode signal TM, block forcedly-activating signal BFAT₆ and capacity mode signal CM₈ all of which are output from the control circuit 3 and block selecting signals BS₆₁₁, BS₆₂₂, BS₆₄₄ supplied from the block selecting signal generating circuit 18 ₆, generates the row address latch signal RLT₆ used to temporarily hold row addresses decoded by the row decoder 10 (see FIG. 3) and feeds them to the sixth block.

FIG. 28 is a schematic block diagram showing one example of configurations of the row address latch signal generating circuit 19 ₆. In FIG. 28, same reference numbers are assigned to corresponding parts in FIG. 24 and their descriptions are omitted accordingly. In the row address latch signal generating circuit 19 ₆ shown in FIG. 28, instead of the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄ and the block forcedly-activating signal BFAT₅, the block selecting signals BS₆₁₁, BS₆₂₂ and BS₆₄₄ are newly input from the block selecting signal generating circuit 18 ₆ and the block forcedly-activating signal BFAT₆ is newly input from the control circuit 3 and, instead of the row address latch signal RLT₅, the row address latch signal RLT₆ is newly output. That is, configurations of the row address latch signal generating circuit 19 ₆ are the same as those of the row address latch signal generating circuit 19 ₅ except for signals input and output thereto or therefrom. That is, after the row address latch signal generating circuit 19 ₆ has been selected out of 8 pieces of the row address latch signal generating circuits 19 ₁ to 19 ₈ by any one of the low-level block selecting signals BS₆₁₁, BS₆₂₂ and BS₆₄₄, the high-level row address latch signal RLT₆ is output with timing in which the first control signals FIRC₁ to FIRC₃ change to go high, and is then fed to the sixth block. Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₆₁₁, BS₆₂₂ and BS₆₄₄ and the first control signal FIRC₁ to FIRC₃, with timing in which the block forcedly-activating signal BFAT₆ changes to go high, the high-level row address latch signal RLT₈ is output.

The activating signal generating circuit 20 ₆ shown in FIG. 26, based on the second control signals SECC₁ to SECC₃, third control signals THIC₁ to THIC₃, fourth control signals FORC₁₁ to FORC₁₃ and FORC₂₁ to FORC₂₃, test mode signal TM, test clock TCK, block forcedly-activating signal BFAT₆ and capacity mode signal CM₈ all of which are fed from the control circuit 3 and the block selecting signals BS₆₁₁, BS₆₂₂ and BS₆₄₄ fed from the block selecting signal generating circuit 18 ₆, generates the sub-word activating signal SWAT₆ used to activate sub-word lines of the MCA making up the sixth block contained in the memory block 1, two kinds of SA activating signals SAAT₁₆ and SAAT₂₆ used to activate two SAs making up the, sixth block contained in the memory block 1 and the main-word timing control signal MTC₆ used to control timing with which the row decoder 10 outputs the main-word activating signal MWAT, and feeds them to the sixth block.

FIG. 29 is a schematic block diagram showing one example of configurations of the activating signal generating circuit 20 ₆. In FIG. 29, same reference numbers are assigned to corresponding parts in FIG. 25 and their descriptions are omitted accordingly. In the activating signal generating circuit 20 ₆ shown in FIG. 29, instead of the block selecting signal BS₅₁₁, BS₅₂₂ and BS₅₄₄ and the block activating designation signal BFAT₅, the block selecting signal BS₆₁₁, BS₆₂₂ and BS₆₄₄ are newly input from the block selecting signal generating circuit 18 ₆ and the block activating designation signal BFAT₆ from the control circuit 3 and instead of the sub-word activating signal SWAT₅, SA activating signals SAAT₁₅ and SAAT₂₅ and main-word timing control signal MTC₅, sub-word activating signal SWAT₆, SA activating signals SAAT₁₆ and SAAT₂₆ and the main-word timing control signal MTC₆are newly output. That is, configurations of the activating signal generating circuit 20 ₆ are the same as those of the activating signal generating circuit 20 ₅ except for signals input and output thereto or therefrom.

Therefore, after the activating signal generating circuit 20 ₅ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₆₁₁, BS₆₂₂ and BS₆₄₄, the high-level main-word timing control signal MTC₆ is output with timing in which any one of the second control signals SECC₁, SECC₂ and SECC₃ changes to go high, and is then fed to the sixth block. Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₆₁₁, BS₆₂₂ and BS₆₄₄ and the second control signal SECC₁ to SECC₃, with timing in which the block forcedly-activating signal BFAT₆ changes to go high, the high-level main-word timing control signal MTC₆ is output.

Moreover, after the activating signal generating circuit 20 ₆ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₆₁₁, BS₆₂₂ and BS₆₄₄, the high-level main-word timing control signal MTC₆ is output with timing in which any one of the third control signals THIC₁, THICS₂ and THIC₃ changes to go high, and is then fed to the sixth block. Also, at a time of the test, the test clock TCK is first fed and, after the block forcedly-activating signal BFAT₆ has risen to go high at a time of a sixth rise of the test clock TCK, an output signal from the SR latch 330 changes to go low at a time of a sixth fall of the test clock TCK. Therefore, a high-level sub-word activating signal SWAT₆ is output, irrespective of supply of the block selecting signals BS₆₁₁, BS₆₂₂ and BS₆₄₄ and the third control signal THIC₁ to THIC₃ with timing in which the test clock TCK falls fifth. Furthermore, after the activating signal generating circuit 20 ₆ has been selected from 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₆₁₁, BS₆₂₂ and BS₆₄₄, the high-level SA activating signals SAAT₁₆ and SAAT₂₆ are sequentially output with timing in which the fourth control signals FORC₁₁, FORC₂₁, FORC₁₂ and FORC₂₂ sequentially change to go high.

The block activating section 16 ₇, as shown in FIG. 30, includes a block selecting signal generating circuit 18 ₇, a row address latch signal generating circuit 19 ₇ and an activating signal generating circuit 20 ₇.

The block selecting signal generating circuit 18 ₇, based on the block activating designation signals ATD₁, ATD₅ and ATD₁₃ fed from the refresh decoder 15, latch signals LT₁, LT₂ and LT₄, reversed latch signals /LT₁, /LT₂ and /LT₄, refresh mode signal RM₀₅, bank mode signals BM₁, BM₂ and BM₄ and capacity mode signal CM₈ all of which are fed from the control circuit 3, generates any one of a block selecting signal BS₇₁₁ used to activate the seventh block, if the memory block 1 is made up of one bank, by using all blocks belonging to the bank being operated, a block selecting signal BS₇₂₂ used to activate the seventh block, if the memory block 1 is made up of two banks, by using all blocks belonging to the second bank and a block selecting signal BS₇₄₄ used to activate the seventh block, if the memory block 1 is made up of four banks, by using all blocks belonging to the fourth bank.

FIG. 31 is a schematic block diagram showing one example of configurations of the block selecting signal generating circuit 18 ₇. In FIG. 31, same reference numbers are assigned to corresponding parts in FIG. 23 and their descriptions are omitted accordingly. In the block selecting signal generating circuit 18 ₇ shown in FIG. 31, instead of the block activating designation signals ATD₃ and ATD₇, latch signal LT₃ and reversed latch signal /LT₃ shown in FIG. 23, the block activating designation signals ATD₅ and ATD₁₃ are newly input and, instead of the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄, block selecting signals BS₇₁₁, BS₇₂₂ and BS₇₄₄ are newly output. That is, configurations of the block selecting signal generating circuit 18 ₇ are the same as those of the block selecting signal generating circuit 18 ₅ except for signals input and output thereto or therefrom.

Next, the row address latch signal generating circuit 19 ₇ shown in FIG. 30, based on the first control signals FIRC₁, FIRT₂ and FIRC₃, test mode signal TM, block forcedly-activating signal BFAT₇ and capacity mode signal CM₈ all of which are output from the control circuit 3 and block selecting signals BS₇₁₁, BS₇₂₂, BS₇₄₄ supplied from the block selecting signal generating circuit 18 ₇, generates the row address latch signal RLT₇ used to temporarily hold row addresses decoded by the row decoder 10 (see FIG. 3) and feeds them to the seventh block.

FIG. 32 is a schematic block diagram showing one example of configurations of the row address latch signal generating circuit 19 ₇. In FIG. 32, same reference numbers are assigned to corresponding parts in FIG. 24 and their descriptions are omitted accordingly. In the row address latch signal generating circuit 19 ₇ shown in FIG. 32, instead of the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄ and the block forcedly-activating signal BFAT₅ shown in FIG. 24, the block selecting signals BS₇₁₁, BS₇₂₂ and BS₇₄₄ are newly input from the block selecting signal generating circuit 18 ₇ and, at the same time, the block forcedly-activating signal BFAT₇ is newly input from the control circuit 3 and, instead of the row address latch signal RLT₅, the row address latch signal RLT₇is newly output. That is, configurations of the row address latch signal generating circuit 19 ₇ are the same as those of the row address latch signal generating circuit 19 ₅ except for signals input and output thereto or therefrom. That is, after the row address latch signal generating circuit 19 ₇ has been selected out of 8 pieces of the row address latch signal generating circuits 19 ₁ to 19 ₈ by any one of the low-level block selecting signals BS₇₁₁, BS₇₂₂ and BS₇₄₄, the high-level row address latch signal RLT₇ is output with timing in which the first control signals FIRC₁, FIRC₂ and FIRC₄ change to go high, and is then fed to the seventh block. Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₇₁₁, BS₇₂₂ and BS₇₄₄ and the first control signal FIRC₁, FIRC₂ and FIRC₄, with timing in which the block forcedly-activating signal BFAT₇ changes to go high, the high-level row address latch signal RLT₇ is output.

The activating signal generating circuit 20 ₇ shown in FIG. 30, based on the second control signals SECC₁, SECC₂ and SECC₄, third control signals THIC₁, THIC₂ and THIC₄, fourth control signals FORC₁₁, FORC₁₂, FORC₁₄, FORC₂₁, FORC₂₂, FORC₂₄, test mode signal TM, test clock TCK, block forcedly-activating signal BFAT₇ and capacity mode signal CM₈ all of which are fed from the control circuit 3 and the block selecting signals BS₇₁₁, BS₇₂₂ and BS₇₄₄ fed from the block selecting signal generating circuit 18 ₇, generates the sub-word activating signal SWAT₇ used to activate sub-word lines of the MCA making up the seventh block contained in the memory block 1, two kinds of SA activating signals SAAT₁₇ and SAAT₂₇ used to activate two SAs making up the seventh block contained in the memory block 1 and the main-word timing control signal MTC₇ used to control timing with which the row decoder 10 outputs the main-word activating signal MWAT, and feeds them to the seventh block.

FIG. 33 is a schematic block diagram showing one example of configurations of the activating signal generating circuit 20 ₇. In FIG. 33, same reference numbers are assigned to corresponding parts in FIG. 25 and their descriptions are omitted accordingly. In the activating signal generating circuit 20 ₇ shown in FIG. 33, instead of the block selecting signal BS₅₁₁, BS₅₂₂ and BS₅₄₄, second control signal SECC₃, third control signal THIC₃, fourth control signals FORC₁₃ and FORC₂₃ and block forcedly-activating signal BFAT₅ shown in FIG. 25, the block selecting signal BS₇₁₁, BS₇₂₂ and BS₇₄₄ are newly input from the block selecting signal generating circuit 18 ₇ and, at the same time, the second control signal SECC₄, third control signal THIC₄, fourth control signals FORC₁₄ and FORC₂₄ and block forcedly-activating signal BFAT₇ are newly input from the control circuit 3 and, instead of the sub-word activating signal SWAT₅, SA activating signals SAAT₁₅ and SATT₂₅ and main-word timing control MTC₅, sub-word activating signal SWAT₇, SA activating signals SAAT₁₇ and SATT₂₇ and main-word timing control MTC₇ are newly output. That is, configurations of the activating signal generating circuit 20 ₇ are the same as those of the activating signal generating circuit 20 ₅ except for signals input and output thereto or therefrom.

Therefore, after the activating signal generating circuit 20 ₇ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₇₁₁, BS₇₂₂ and BS₇₄₄, the high-level main-word timing control signal MTC₇ is output with timing in which any one of the second control signals SECC₁, SECC₂ and SECC₄ changes to go high, and is then fed to the seventh block. Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₇₁₁, BS₇₂₂ and BS₇₄₄ and the second control signal SECC₁, SECC₂ and SECC₄, with timing in which the block forcedly-activating signal BFAT₇ changes to go high, the high-level main-word timing control signal MTC₇ is output.

Moreover, after the activating signal generating circuit 20 ₇ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₇₁₁, BS₇₂₂ and BS₇₄₄, the high-level sub-word timing control signal SWAT₇ is output with timing in which any one of the third control signals THIC₁, THICS₂ and THIC₄ changes to go high, and is then fed to the seventh block. Also, at a time of the test, the test clock TCK is first fed and, after the block forcedly-activating signal BFAT₇ has risen to go high at a time of a seventh rise of the test clock TCK, an output signal from the SR latch 330 changes to go low at a time of a seventh fall of the test clock TCK. Therefore, a high-level sub-word activating signal SWAT₇ is output, irrespective of supply of the block selecting signals BS₇₁₁, BS₇₂₂ and BS₇₄₄ and the third control signal THIC₁, THIC₂ and THIC₄ with timing in which the test clock TCK falls seventh.

Moreover, after the activating signal generating circuit 20 ₇ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₇₁₁, BS₇₂₂ and BS₇₄₄, the high-level SA activating signals SAAT₁₇ and SAAT₂₇ are sequentially output with timing in which the fourth control signals FORC₁₁, FORC₂₁, FORC₁₂ and FORC₂₂ sequentially change to go high.

The block activating section 16 ₈, as shown in FIG. 34, includes a block selecting signal generating circuit 18 ₈, a row address latch signal generating circuit 19 ₈ and an activating signal generating circuit 20 ₈. The block selecting signal generating circuit 18 ₈, based on the block activating designation signals ATD₂, ATD₆ and ATD₁₄ fed from the refresh decoder 15, latch signals LT₁, LT₂ and LT₄, reversed latch signals /LT₁, /LT₂ and /LT₄, refresh mode signal RM₀₅, bank mode signals BM₁, BM₂ and BM₄ and capacity mode signal CM₈ all of which are fed from the control circuit 3, generates any one of a block selecting signal BS₈₁₁ used to activate the eighth block, if the memory block 1 is made up of one bank, by using all blocks belonging to the bank being operated, a block selecting signal BS₈₂₂ used to activate the eighth block, if the memory block 1 is made up of two banks, by using all blocks belonging to the second bank and a block selecting signal BS₈₄₄ used to activate the eighth block, if the memory block 1 is made up of four banks, by using all blocks belonging to the fourth bank.

FIG. 35 is a schematic block diagram showing one example of configurations of the block selecting signal generating circuit 18 ₈. In FIG. 35, same reference numbers are assigned to corresponding parts in FIG. 23 and their descriptions are omitted accordingly. In the block selecting signal generating circuit 18 ₈ shown in FIG. 35, instead of the block activating designation signals ATD₁, ATD₃ and ATD₇, latch signal LT₃ and reversed latch signal /LT₃ shown in FIG. 23, the block activating designation signals ATD₂, ATD₆ and ADT₁₄, latch signal LT₄ and reversed latch signal /LT₄ are newly input and, instead of the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄, the block selecting signals BS₈₁₁, BS₈₂₂ and BS₈₄₄ are newly output. That is, configurations of the block selecting signal generating circuit 18 ₈ are the same as those of the block selecting signal generating circuit 18 ₅ except for signals input and output thereto or therefrom.

Next, the row address latch signal generating circuit 19 ₈ shown in FIG. 34, based on the first control signals FIRC₁, FIRT₂ and FIRC₄, test mode signal TM, block forcedly-activating signal BFAT₈ and capacity mode signal CM₈ all of which are output from the control circuit 3 and block selecting signals BS₈₁₁, BS₈₂₂, BS₈₄₄ supplied from the block selecting signal generating circuit 18 ₈, generates the row address latch signal RLT₈ used to temporarily hold row addresses decoded by the row decoder 10 (see FIG. 3) and feeds them to the eighth block.

FIG. 36 is a schematic block diagram showing one example of configurations of the row address latch signal generating circuit 19 ₈. In FIG. 36, same reference numbers are assigned to corresponding parts in FIG. 24 and their descriptions are omitted accordingly. In the row address latch signal generating circuit 19 ₈ shown in FIG. 36, instead of the block selecting signals BS₅₁₁, BS₅₂₂ and BS₅₄₄ and the block forcedly-activating signal BFAT₅ shown in FIG. 24, the block selecting signals BS₈₁₁, BS₈₂₂ and BS₈₄₄ are newly input from the block selecting signal generating circuit 18 ₈ and, at the same time, the block forcedly-activating signal BFAT₈ is newly input from the control circuit 3 and, instead of the row address latch signal RLT₅, the row address latch signal RLT₈ is newly output. That is, configurations of the row address latch signal generating circuit 19 ₈ are the same as those of the row address latch signal generating circuit 19 ₅ except for signals input and output thereto or therefrom. That is, after the row address latch signal generating circuit 19 ₈ has been selected out of 8 pieces of the row address latch signal generating circuits 19 ₁ to 19 ₈ by any one of the low-level block selecting signals BS₈₁₁, BS₈₂₂ and BS₈₄₄, the high-level row address latch signal RLT₈ is output with timing in which the first control signals FIRC₁, FIRC₂ and FIRC₄ change to go high, and is then fed to the eighth block. Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₈₁₁, BS₈₂₂ and BS₈₄₄ and the first control signal FIRC₁, FIRC₂ and FIRC₄, with timing in which the block forcedly-activating signal BFAT₈ changes to go high, the high-level row address latch signal RLT₈ is output.

The activating signal generating circuit 20 ₈ shown in FIG. 34, based on the second control signals SECC₁, SECC₂ and SECC₄, third control signals THIC₁, THIC₂ and THIC₄, fourth control signals FORC₁₁, FORC₁₂, FORC₁₄, FORC₂₁, FORC₂₂, FORC₂₄, test mode signal TM, test clock TCK, block forcedly-activating signal BFAT₈ and capacity mode signal CM₈ all of which are fed from the control circuit 3 and block selecting signals BS₈₁₁, BS₈₂₂ and BS₈₄₄ fed from the block selecting signal generating circuit 18 ₈, generates the sub-word activating signal SWAT₈ used to activate sub-word lines of the MCA making up the eighth block contained in the memory block 1, two kinds of SA activating signals SAAT₁₈ and SAAT₂₈ used to activate two SAs making up the eighth block contained in the memory block 1 and the main-word timing control signal MTC₈ used to control timing with which the row decoder 10 outputs the main-word activating signal MWAT, and feeds them to the eighth block.

FIG. 37 is a schematic block diagram showing one example of configurations of the activating signal generating circuit 20 ₈. In FIG. 37, same reference numbers are assigned to corresponding parts in FIG. 25 and their descriptions are omitted accordingly. In the activating signal generating circuit 20 ₈ shown in FIG. 37, instead of the block selecting signal BS₅₁₁, BS₅₂₂ and BS₅₄₄, second control signal SECC₃, third control signal THIC₃, fourth control signals FORC₁₃ and FORC₂₃ and block forcedly-activating signal BFAT₅ shown in FIG. 25, the block selecting signal BS₈₁₁, BS₈₂₂ and BS₈₄₄ are newly input from the block selecting signal generating circuit 18 ₈ and, at the same time, the second control signal SECC₄, third control signal THIC₄, fourth control signals FORC₁₄ and FORC₂₄ and block forcedly-activating signal BFAT₇ are newly input from the control circuit 3 and, instead of the sub-word activating signal SWAT₅, SA activating signals SAAT₁₅ and SATT₂₅ and main-word timing control MTC₅, the sub-word activating signal SWAT₈, SA activating signals SAAT₁₈ and SATT₂₈ and main-word timing control MTC₈ are newly output. That is, configurations of the activating signal generating circuit 20 ₈ are the same as those of the activating signal generating circuit 20 ₅ except for signals input and output thereto or therefrom.

Therefore, after the activating signal generating circuit 20 ₈ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₈₁₁, BS₈₂₂ and BS₈₄₄, the high-level main-word timing control signal MTC₈ is output with timing in which any one of the second control signals SECC₁, SECC₂ and SECC₄ changes to go high, and is then fed to the eighth block. Moreover, at a time of the test, since the test mode signal TM changes to go high, irrespective of supply of the block selecting signals BS₈₁₁, BS₈₂₂ and BS₈₄₄ and the second control signal SECC₁, SECC₂ and SECC₄, with timing in which the block forcedly-activating signal BFAT₈ changes to go high, the high-level main-word timing control signal MTC₈ is output.

Moreover, after the activating signal generating circuit 20 ₈ has been selected out of 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the low-level block selecting signals BS₈₁₁, BS₈₂₂ and BS₈₄₄, the high-level sub-word timing control signal SWAT₈ is output with timing in which any one of the third control signals THIC₁, THICS₂ and THIC₄ changes to go high, and is then fed to the eighth block. Also, at a time of the test, the test clock TCK is first fed and, after the block forcedly-activating signal BFAT₈ has risen to go high at a time of an eighth rise of the test clock TCK, an output signal from the SR latch 330 changes to go low at a time of an eighth fall of the test clock TCK. Therefore, the high-level sub-word activating signal SWAT₈ is output, irrespective of supply of the block selecting signals BS₈₁₁, BS₈₂₂ and BS₈₄₄ and the third control signal THIC₁, THIC₂ and THIC₄ with timing in which the test clock TCK falls eighth.

Moreover, after the activating signal generating circuit 20 ₈ has been selected from 8 pieces of the activating signal generating circuits 20 ₁ to 20 ₈ by any one of the high-level block selecting signals BS₈₁₁, BS₈₂₂ and BS₈₄₄, high-level SA activating signals SAAT₁₈ and SAAT₂₈ are sequentially output with timing in which the fourth control signals FORC₁₁, FORC₂₁, FORC₁₂ and FORC₂₂ change sequentially to go high.

Next, operations of the DRAM having configurations described above are explained below by referring to FIG. 38 to FIG. 45. First, a brief description of the DRAM will be given by referring to FIG. 38. The control circuit 3, by causing the latch signals LT₁ to LT₄, the number of which corresponds to storage capacity, numbers of banks and numbers of rows of memory cell arrays to be refreshed which are all set by the system designer, to sequentially rise to go high (see FIG. 38[1]) and by causing each of corresponding reversed latch signals /LT to simultaneously and sequentially fall to go low (not shown), temporarily holds each of corresponding block selecting signals BS obtained before being reversed in each of block selecting signal generating circuits 18 ₁ to 18 ₈ making up each of the block activating sections 16 ₁ to 16 ₈. Then, the control circuit 3 causes the first control signals FIRC₁ to FIRC₄, second control signals SECC₁ to SECC₄, third control signals THIC₁ to THIC₄, 2 kinds of the fourth control signals FORC₁ to FORC₁₄ and FORC₂₁ to FORC₂₄, the number and kind of which correspond to storage capacity, the number of banks and the number of rows of memory cell arrays to be refreshed which are set by the system designer, to sequentially rise to go high (see FIG. 38 [2] to [6]).

As a result, each of the block selecting signal generating circuits 18 ₁ to 18 ₈, since the transfer gate is turned OFF in response to the rise of each of the corresponding latch signals LT₁ to LT₄ and the fall of the reversed latch signal /LT, while the transfer gate is in the OFF state, latches the block selecting signal BS obtained before being reversed. Therefore, since the corresponding selecting signal BS is fed as a low level, each of the selected row address latch signal generating circuits 19 ₁ to 19 ₈, while each of the corresponding first control signals FIRC₁ to FIRC₄ remains at a high level (see FIG. 38 [2]), generates each of the corresponding row address latch signals RLT₁ to RLT₈ (see FIG. 38 [8]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3). Similarly, since the corresponding block selecting signal BS is fed as a low level, each of the activating signal generating circuits 20 ₁ to 20 ₈, while each of the corresponding second control signals SECC₁ to SECC₄ remains at a high level (see FIG. 38 [3]), generates each of the corresponding main-word timing control signals MTC₁ to MTC₈ (see FIG. 38 [8]) and feeds them to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3) and, while each of the third control signals THIC₁ to THIC₄ remains at a high level (see FIG. 38 [4]), generates each of the corresponding sub-word activating signals SWAT₁ to SWAT₈ (see FIG. 38 [9]) and then feeds them to each of the sub-word lines of the corresponding MCA and further, while the two kinds of the fourth control signals FORC₁₁ to FORC₁₄ and FORC₂₁ to FORC₂₄ (see FIG. 38 [5] and [6]) remain at a high level, generates the corresponding two kinds of the SA activating signals SAAT₁₁ to SAAT₁₈ and SAAT₂₁ to SAAT₂₈ (see FIG. 38 [10] and [11]) and then feeds them to two SAs making up the corresponding block.

Next, normal operations of the DRAM will be described in detail by referring to FIG. 39 to FIG. 41. First, in the embodiment, since the system designer sets the storage capacity at 8M bits, numbers of banks at 4 and numbers of rows of memory cell arrays to be refreshed at 1K, the control circuit 3 outputs all the capacity mode signal CM₈, bank mode signal BM₄ and refresh mode signal RM₁₀ as high-level signals as shown in FIG. 39 [1] to [3] and all the capacity mode signals CM₂ and CM₄, bank mode signals BM₁ and BM₂, refresh mode signals RM₀₅, RM₂₀ and RM₄₀ as low level signals (not shown). Moreover, the control circuit 3, since the number of rows of memory cell arrays to be refreshed is set at 1K, feeds the row address higher-bit signal RAD₁₀ and the reversed row address higher-bit signal /RAD₁₀ out of address signals AD supplied from outside to the activating circuit 4, however, does not feed the row address higher-bit signals RAD₁₁ and RAD₁₂ and the reversed row address higher-bit signals /RAD₁₁ and /RAD₁₂ (see FIG. 39 [4] to [9]) to the activating circuit 4. Furthermore, the control circuit 3, since it is in a normal operation, keeps the test mode signal TM and the block forcedly-activating signals BFAT₁ to BFAT₈ at a low level and does not supply the test clock TCK. Next, the control circuit 3, after specified time has elapsed following the supply of the high-level reversed row address higher-bit signal /RAD₁₀, makes the latch signal LT₁ rise to go high (see FIG. 39 [10]) and, at the same time, makes the reversed latch signal /LT₁ fall to go low (not shown). On the other hand, the refresh decoder 15 shown in FIG. 5, though not shown, based on the high-level refresh mode signal RM₁₀ and high-level reversed row address higher-bit signal /RAD₁₀, generates the block activating designation signal ATD₁ and feeds it to the block selecting signal generating circuits 18 ₁, 18 ₃, 18 ₅ and 18 ₇. This causes the block selecting signal generating circuit 18 ₁ to output the block selecting signal BS₁₁₄ as a low level and, while the latch signal LT₁ remains at a high level, holds the block selecting signal BS₁₁₄ as the low-level signal (not shown), however, since neither the high-level latch signals LT₂ to LT₄ nor low-level reversed latch signals /LT₂ to /LT₄ are fed, each of the block selecting signals BS₃₂₄, BS₅₄₄ and BS₇₄₄ is output as a low level from each of the block selecting signal generating circuits 18 ₃, 18 ₅ and 18 ₇ respectively, only while the block activating designation ATD₁ is being supplied, that is, only while the high-level reversed row address higher-bit signal /RAD₁₀ is being supplied (not shown).

Next, the control circuit 3, after specified time has elapsed, makes the first control signal FIRC₁, second control signal SECC₁, third control signal THIC₁ and two kinds of fourth control signals FORC₁₁ and FORC₂₁ sequentially rise to go high and holds them at a high level for specified time (see FIG. 40 [1] and [13] and FIG. 41 [1] and [5]). As a result, the row address latch signal generating circuit 19 ₁ generates the high-level row address latch signal RLT₁ while the first control signal FIRC₁ remains at a high level (see FIG. 39 [14]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6. On the other hand, though each of the row address latch signal generating circuits 19 ₃, 19 ₅ and 19 ₇ is fed respectively with each of the low-level block selecting signal BS₃₂₄, BS₅₄₄ and BS₇₄₄ only while the high-level reversed row address higher-bit signal /RAD₁₀ is being fed, since the high-level control signals FIRC₂ to FIRC₄ are not fed, each of the row address latch signal generating circuits 19 ₃, 19 ₅ and 19 ₇ does not output the high-level row address latch signals RLT₃, RLT₅ and RLT₇ (see FIG. 39 [20], [22] and [24]. Similarly, the activating signal generating circuit 20 ₁, while the second control signal SECC₁ remains at a high level (see FIG. 40 [1]), generates the main-word timing control signal MTC₁ (see FIG. 40 [5]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3) and, while the third control signal THIC₁ remains at a high level (see FIG. 40 [13]), generates the sub-word activating signal SWAT₁ (see FIG. 40 [17] ) and then feeds it to sub-word lines of corresponding MCA and, while the two kinds of the corresponding control signals FORC₁₁ and FORC₂₁ remain at a high level (see FIG. 41 [1] and [5]), generates the two kinds of the SA activating signals SAAT₁₁ and SAAT₂₁ (see FIG. 41 [9] and [17] ) and then feeds them to two pieces of the SAs 9 ₁₁ and 9 ₁₂ making up the first block using all blocks belonging to the bank 7 ₁ shown in FIG. 2. On the other hand, though each of the activating signal generating circuits 20 ₃, 20 ₅ and 20 ₇ is fed with each of the low-level block selecting signals BS₃₂₄, BS₅₄₄ and BS₇₄₄ only while the high-level reversed row address higher-bit signal /RAD₁₀ is supplied, since high-level second control signals SECC₂ to SECC₄, high-level third control signals THIC₂ to THIC₄ and high-level fourth control signals FORC₁₂ to FORC₁₄ and FORC₂₂ to FORC₂₄ are not supplied, each of the activating signal generating circuits 20 ₃, 20 ₅ and 20 ₇ does not output the high-level main-word timing control signal MTC₃, MTC₅ and MTC₇, high-level sub-word activating signal SWAT₃, SWAT₅ and SWAT₇ and high-level SA activating signals SAAT₁₃, SAAT₂₃ and SAAT₁₅, SAAT₂₅, SAAT₁₇ and SAAT₂₇ (see FIG. 40 [7], [9], [11], [19], [21] and [23], and FIG. 41 [11], [13], [15], [19], [21] and [23]).

The control circuit 3, after having made the first control signal FIRC₁ fall to go low (see FIG. 39 [14]), by causing the third control signal THIC₁, two kinds of the fourth control signals FORC₁₁ and FORC₂₁ to fall simultaneously to go low (see FIG. 40 [13] and FIG. 41 [1] and [5]), makes both the sub-word activating signal SWAT₁ and two kinds of SA activating signals SAAT₁₁ and SAAT₂₁ simultaneously fall (see FIG. 40 [17] and see FIG. 41 [9]). Then, the control circuit 3, by making the second control signal SECC₁ fall to go low (see FIG. 40 [1]), after completion of the activation of the first block by using all blocks belonging to the bank 7 ₁, makes the latch signal LT₁ fall to go low (see FIG. 39 [10]) and the reversed latch signal /LT₁ rise to go high (not shown).

Next, the control circuit 3, after specified time has elapsed following the supply of the high-level row address higher-bit signal RAD₁₀, makes the latch signal LT₁ rise to go high (see FIG. 39 [10]) and, at the same time, makes the reversed latch signal /LT₁ fall to go low (not shown). On the other hand, the refresh decoder 15 shown in FIG. 5, though not shown, based on the high-level refresh mode signal RM₁₀ and high-level row address higher-bit signal RAD₁₀, generates the block activating designation signal ATD₂ and feeds it to the block selecting signal generating circuits 18 ₂, 18 ₄, 18 ₆ and 18 ₈. This causes the block selecting signal generating circuit 18 ₂ to output the block selecting signal BS₂₁₄ as a low level and, while the latch signal LT₁ remains at a high level, holds the block selecting signal BS₂₁₄ as the low-level signal (not shown), however, since neither the high-level latch signals LT₂ to LT₄ nor low-level reversed latch signals /LT₂ to /LT₄ are fed, each of the block selecting signals BS₄₂₄, BS₆₄₄ and BS₈₄₄ is output as a low level from each of the block selecting signal generating circuits 18 ₄, 18 ₆ and 18 ₈ respectively, only while the block activating designation ATD₂ is being supplied, that is, only while the high-level row address higher-bit signal RAD₁₀ is being supplied (not shown).

Next, the control circuit 3, after specified time has elapsed, makes the first control signal FIRC₁, second control signal SECC₁, third control signal THIC₁ and two kinds of fourth control signals FORC₁₁ and FORC₂₁ sequentially rise to go high (see FIG. 39 [14], FIG. 40 [1] and [13] and FIG. 41 [1] and [5]). As a result, the row address latch signal generating circuit 19 ₂ generates the high-level row address latch signal RLT₂ (see FIG. 39 [19]) while the first control signal FIRC₁ remains at a high level (see FIG. 39 [14]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3). On the other hand, though each of the row address latch signal generating circuits 19 ₄, 19 ₆ and 19 ₈ is fed respectively with each of the low-level block selecting signal BS₄₂₄, BS₆₄₄ and BS₈₄₄ only while the high-level row address higher-bit signal RAD₁₀ is being fed, since the high-level control signals FIRC₂ to FIRC₄ are not fed, each of the row address latch signal generating circuits 19 ₄, 19 ₆ and 19 ₈ does not output the high-level row address latch signals RLT₄, RLT₆ and RLT₈ (see FIG. 39 [21], [23] and [25]). Similarly, the activating signal generating circuit 20 ₂, while the second control signal SECC, remains at a high level (see FIG. 40 [1]), generates the main-word timing control signal MTC₂ (see FIG. 40 [6]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3) and, while the third control signal THIC₁ remains at a high level (see FIG. 40 [13]), generates the sub-word activating signal SWAT₂ (see FIG. 40 [18]) and then feeds it to sub-word lines of corresponding MCA and, while the two kinds of the corresponding control signals FORC₁₁ and FORC₂₁ remain at a high level (see FIG. 41 [1] and [5]), generates the two kinds of the SA activating signals SAAT₁₂ and SAAT₂₂ (see FIG. 41 [10] and [18]) and then feeds them to two pieces of the SAs 9 ₂₁ and 9 ₂₂ making up the second block using all blocks belonging to the bank 7 ₁ shown in FIG. 2. On the other hand, though each of the activating signal generating circuits 20 ₄, 20 ₆ and 20 ₈ is fed with each of the low-level block selecting signals BS₄₂₄, BS₆₄₄ and BS₈₄₄ only while the high-level row address higher-bit signal RAD₁₀ is supplied, since high-level second control signals SECC₂ to SECC₄, high-level third control signals THIC₂ to THIC₄ and high-level fourth control signals FORC₁₂ to FORC₁₄ and FORC₂₂ to FORC₂₄ are not supplied, each of the activating signal generating circuits 20 ₄, 20 ₆ and 20 ₈ does not output the high-level main-word timing control signal MTC₄, MTC₆ and MTC₈, high-level sub-word activating signal SWAT₄, SWAT₆ and SWAT₈ and high-level SA activating signals SAAT₂₄, SAAT₁₆ and SAAT₂₆, SAAT₁₈ and SAAT₂₈ (see FIG. 40 [8], [10], [12], [20], [22] and [24], and FIG. 41 [12], [14], [16], [20], [22] and [24]). Then, the control circuit 3, after having made the first control signal FIRC₁ fall to go low (see FIG. 39 [14]), by causing the third control signal THIC₁, two kinds of the fourth control signals FORC₁₁ and FORC₂₁ to fall simultaneously to go low (see FIG. 40 [13] and FIG. 41 [1] and [5]), makes both the sub-word activating signal SWAT₂ and two kinds of SA activating signals SAAT₁₂ and SAAT₂₂ simultaneously fall (see FIG. 40 [18] and see FIG. 41 [10]). Then, the control circuit 3, by making the second control signal SECC₁ fall to go low (see FIG. 40 [1]), after completion of the activation of the second block by using all blocks belonging to the bank 7 ₁, makes the latch signal LT₁ fall to go low (see FIG. 39 [10]) and the reversed latch signal /LT₁ rise to go high (not shown).

Thereafter, every time the high-level reversed row address higher-bit signal /RAD₁₀ and high-level row address higher-bit signal RAD₁₀ are supplied, by repeating the same operations as described above on the latch signals LT₂ to LT₄, reversed latch signals /LT₂ to /LT₄, first control signals FIRC₂ to FIRC₄, second control signals SECC₂ to SECC₄, third control signals THIC₂ to THIC₄ and two kinds of the fourth control signals FORC₁₂ to FORC₁₄ and FORC₂₂ to FORC₂₄, the third to eighth blocks are sequentially activated. Moreover, operations of writing and reading of data, of refreshing or a like are almost the same as those of the conventional DRAM and their descriptions are omitted accordingly.

Next, operations in which a plurality of blocks belonging to a plurality of banks of the DRAM are almost simultaneously activated will be described by referring to FIG. 42 to FIG. 44. First, in the embodiment, since the system designer sets the storage capacity at 8M bits, numbers of banks at 4 and numbers of rows of memory cell arrays to be refreshed at 1K, the control circuit 3 outputs all the capacity mode signal CM₈, bank mode signal BM₄ and refresh mode signal RM₁₀ as a high-level as shown in FIG. 42 [1] to [3] and all the capacity mode signals CM₂ and CM₄, bank mode signals BM₁ and BM₂, refresh mode signals RM₀₅, RM₂₀ and RM₄₀ as a low level (not shown). Moreover, the control circuit 3, since the number of rows of memory cell arrays to be refreshed is set at 1K, feeds the row address higher-bit signal RAD₁₀ and reversed row address higher-bit signal /RAD₁₀ out of address signals AD supplied from outside to the activating circuit 4 and does not feed the row address higher-bit signal RAD₁₁, RAD₁₂ and reversed row address higher-bit signal /RAD₁₁ and /RAD₁₂ (see FIG. 42 [4] to [9]). Furthermore, the control circuit 3, since it is in a normal operation, keeps the test mode signal TM and the block forcedly-activating signals BFAT₁ to BFAT₆ at a low level and does not supply the test clock TCK.

Next, the control circuit 3, after specified time has elapsed following the supply of the high-level reversed row address higher-bit signal /RAD₁₀, makes the latch signal LT₁ rise to go high (see FIG. 40 [10]) and, at the same time, makes the reversed latch signal /LT₁ fall to go low (not shown). On the other hand, the refresh decoder 15 shown in FIG. 5, though not shown, based on the high-level refresh mode signal RM₁₀ and high-level reversed row address higher-bit signal /RAD₁₀, generates the block activating designation signal ATD₁ and feeds it to the block selecting signal generating circuits 18 ₁, 18 ₃, 18 ₅ and 18 ₇. This causes the block selecting signal generating circuit 18 ₁ to output the block selecting signal BS₁₁₄ as a low level and, while the latch signal LT₁ remains at a high level, holds the block selecting signal BS₁₁₄ as the low-level signal (not shown), however, since neither the high-level latch signals LT₂ to LT₄ nor low-level reversed latch signals /LT₂ to /LT₄ are fed, each of the block selecting signals BS₃₂₄, BS₅₄₄ and BS₇₄₄ is output as a low level from each of the block selecting signal generating circuits 18 ₃, 18 ₅ and 18 ₈ respectively, only while the block activating designation ATD₁ is being supplied, that is, only while the high-level reversed row address higher-bit signal /RAD₁₀ is being supplied (not shown).

Next, the control circuit 3, after specified time has elapsed, makes the first control signal FIRC₁, second control signal SECC₁, third control signal THIC₁ and two kinds of fourth control signals FORC₁₁ and FORC₂₁ sequentially rise to go high (see FIG. 42 [14]). (see FIG. 42 [14], FIG. 43 [1] and [13] and FIG. 44 [1] and [5]). As a result, the row address latch signal generating circuit 19 ₁ generates the high-level row address latch signal RLT₁ (see FIG. 42 [18]) while the first control signal FIRC₁ remains at a high level (see FIG. 42 [14]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3). On the other hand, though each of the row address latch signal generating circuits 19 ₃, 19 ₅ and 19 ₇ is fed respectively with each of the low-level block selecting signal BS₃₂₄, BS₅₄₄ and BS₇₄₄ only while the high-level reversed row address higher-bit signal /RAD₁₀ is being fed, since the high-level first control signals FIRC₂ to FIRC₄ are not fed, each of the row address latch signal generating circuits 19 ₃, 19 ₅ and 19 ₇ does not output the high-level row address latch signals RLT₃, RLT₅ and RLT₇ (see FIG. 42 [20], [22] and [24]. Similarly, the activating signal generating circuit 20 ₁, while the second control signal SECC₁ remains at a high level (see FIG. 43 [1]), generates the main-word timing control signal MTC₁ (see FIG. 43 [5]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3) and, while the third control signal THIC₁ remains at a high level (see FIG. 43 [13]), generates the sub-word activating signal SWAT₁ (see FIG. 43 [17]) and then feeds it to sub-word lines of corresponding MCA and, while the two kinds of the corresponding fourth control signals FORC₁₁ and FORC₂₁ remain at a high level (see FIG. 41 [1] and [5]), generates two kinds of the SA activating signals SAAT₁₁ and SAAT₂₁ (see FIG. 44 [9] and [17]) and then feeds them to two SAs 9 ₁₁ and 9 ₁₂ making up the first block by using all the blocks belonging to the bank 7 ₁ shown in FIG. 2. On the other hand, though each of the activating signal generating circuits 20 ₃, 20 ₅ and 20 ₇ is fed with each of the low-level block selecting signals BS₃₂₄, BS₅₄₄ and BS₇₄₄ only while the high-level reversed row address higher-bit signal /RAD₁₀ is supplied, since high-level second control signals SECC₂ to SECC₄, high-level third control signals THIC₂ to THIC₄ and high-level fourth control signals FORC₁₂ to FORC₁₄ and FORC₂₂ to FORC₂₄ are not supplied, each of the activating signal generating circuits 20 ₃, 20 ₅ and 20 ₇ does not output the high-level main-word timing control signal MTC₃, MTC₅ and MTC₇, high-level sub-word activating signal SWAT₃, SWAT₅ and SWAT₇ and high-level SA activating signals SAAT₁₃, SAAT₂₃ and SAAT₁₅, SAAT₂₅, SAAT₁₇ and SAAT₂₇ (see FIG. 43 [7], [9], [11], [19], [21] and [23], and FIG. 44 [11], [13], [15], [19], [21] and [23]).

While the first block is activated by all blocks belonging to the bank 7 ₁ described above, the control circuit 3, after specified time has elapsed following supply of the high-level row address higher-bit signal RAD₁₀, makes the latch signal LT₂ rise to go high (see FIG. 42 [11]) and the reversed latch signal /LT₂ simultaneously fall to go low (not shown). On the other hand, the refresh decoder 15 shown in FIG. 5, though not shown, based on the high-level refresh mode signal RM₁₀ and high-level row address higher-bit signal RAD₁₀, generates the block activating designation signal ATD₂ and feeds it to the block selecting signal generating circuits 18 ₂, 18 ₄, 18 ₆ and 18 ₈. Moreover, the high-level latch signal LT₁ and the low-level reversed latch signal /LT1 continue to be supplied (see FIG. 42 [10]). This causes the block selecting signal generating circuit 18 ₁ to output the low-level block selecting signal BS₁₁₄ (not shown). On the other hand, in the block selecting signal generating circuit 18 ₂, though the block activating designation signal ATD₂ is supplied, since the transfer gate 87 remains in an OFF state due to the high-level latch signal LT₁ and low-level reversed latch signal /LT₁, the block selecting signal BS₂₁₄ is output as a high-level signal (not shown). Furthermore, this causes the block selecting signal generating circuit 18 ₄ to output the block selecting signal BS₄₂₄ as a low level and, while the latch signal LT₂ remains at a high level, holds the block selecting signal BS₄₂₄ as the low-level signal (not shown), however, since neither the high-level latch signals LT₃ and LT₄ nor low-level reversed latch signals /LT₃ and /LT₄ are fed, each of the block selecting signals BS₆₃₄ and BS₈₄₄ is output as a low level from each of the block selecting signal generating circuits 18 ₆ and 18 ₈ respectively, only while the block activating designation ATD₂ is being supplied, that is, only while the high-level row address higher-bit signal RAD₁₀ is being supplied (not shown).

Next, the control circuit 3, after specified time has elapsed, makes the first control signal FIRC₂, second control signal SECC₂, third control signal THIC₂ and two kinds of fourth control signals FORC₁₂ and FORC₂₂ sequentially rise to go high (see FIG. 42 [15], FIG. 43 [15], [14] and FIG. 44 [2] and [6]). As a result, the row address latch signal generating circuit 19 ₄ generates the row address latch signal RLT₁ (see FIG. 42 [21]) while the first control signal FIRC₂ remains at a high level (see FIG. 42 [15]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3). On the other hand, though each of the row address latch signal generating circuits 19 ₆ and 19 ₈ is fed respectively with each of the low-level block selecting signal BS₆₄₄ and BS₈₄₄ only while the high-level row address higher-bit signal RAD₁₀ is being fed, since the high-level first control signals FIRC₃ and FIRC₄ are not fed, each of the row address latch signal generating circuits 19 ₆ and 19 ₈ does not output the high-level row address latch signals RLT₆ and RLT₈ (see FIG. 42 [23] and [25]). Similarly, the activating signal generating circuit 20 ₄, while the second control signal SECC₂ remains at a high level (see FIG. 43 [2]), generates the main-word timing control signal MTC₄ (see FIG. 43 [8]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3) and, while the third control signal THIC₂ remains at a high level (see FIG. 43 [14]), generates the sub-word activating signal SWAT₄ (see FIG. 43 [20]) and then feeds it to sub-word lines of corresponding MCA and, while two kinds of the corresponding fourth control signals FORC₁₂ and FORC₂₂ remain at a high level (see FIG. 44 [2] and [6]), generates two kinds of the SA activating signals SAAT₁₄ and SAAT₂₄ (see FIG. 44 [12] and [20]) and then feeds them to the two SAs 9 ₂₁ and 9 ₂₂ making up the first block by using all the blocks belonging to the bank 7 ₁ shown in FIG. 2. On the other hand, though each of the activating signal generating circuits 20 ₆ and 20 ₈ is fed with each of the low-level block selecting signals BS₆₄₄ and BS₈₄₄ only while the high-level row address higher-bit signal RAD₁₀ is supplied, since high-level second control signals SECC₃ and SECC₄, high-level third control signals THIC₃ and THIC₄ and high-level fourth control signals FORC₁₃ and FORC₁₄ and FORC₂₃ to FORC₂₄ are not supplied, each of the activating signal generating circuits 20 ₆ and 20 ₈ does not output the high-level main-word timing control signal MTC₆ and MTC₈, high-level sub-word activating signal SWAT₆ and SWAT₈ and high-level SA activating signals SAAT₁₆, SAAT₂₆, SAAT₁₈, and SAAT₂₈ (see FIG. 43 [10], [12], [22] and [24] and FIG. 41 [14], [16], [22] and [24]).

While the first block is activated by all blocks belonging to the bank 7 ₁ and the fourth block is activated by all blocks belonging to the bank 7 ₂ described above, the control circuit 3, after specified time has elapsed following supply of the high-level reversed row address higher-bit signal /RAD₁₀, makes the latch signal LT₃ rise to go high (see FIG. 42 [12]) and the reversed latch signal /LT₂ simultaneously fall to go low (not shown). On the other hand, the refresh decoder 15 shown in FIG. 5, though not shown, based on the high-level refresh mode signal RM₁₀ and high-level reversed row address higher-bit signal /RAD₁₀, generates the block activating designation signal ATD₁ and feeds it to the block selecting signal generating circuits 18 ₁, 18 ₃, 18 ₅ and 18 ₇. Moreover, the high-level latch signal LT₁ and LT₂ and the low-level reversed latch signal /LT₁ and /LT₂ continue to be supplied (see FIG. 42 [11]). This causes the block selecting signal generating circuit 18 ₁ and 18 ₄ to output the low-level block selecting signal BS₁₁₄ and BS₄₂₄ (not shown). On the other hand, in the block selecting signal generating circuit 18 ₃, though the block activating designation signal ATD₁ is supplied, since the transfer gate 166 remains in an OFF state due to the high-level latch signal LT₁ and low-level reversed latch signal /LT₁, the block selecting signal BS₃₂₄ is output as a high-level signal (not shown). Furthermore, this causes the block selecting signal generating circuit 18 ₅ to output the block selecting signal BS₅₄₄ as a low level and, while the latch signal LT₃ remains at a high level, holds the block selecting signal BS₅₄₄ as the low-level signal (not shown), however, since neither the high-level latch signal LT₄ nor low-level reversed latch signal /LT₄ are fed, each of the block selecting signal BS₇₄₄ is output as a low level from each of the block selecting signal generating circuits 18 ₇, only while the block activating designation ATD₁ is being supplied, that is, only while the high-level reversed row address higher-bit signal /RAD₁₀ is being supplied (not shown).

Next, the control circuit 3, after specified time has elapsed, makes the first control signal FIRC₃, second control signal SECC₃, third control signal THIC₃ and two kinds of fourth control signals FORC₁₃ and FORC₂₃ sequentially rise to go high (see FIG. 42 [16], FIG. 43 [3], [15] and FIG. 44 [3] and [7]). As a result, the row address latch signal generating circuit 19 ₅ generates the row address latch signal RLT₅ (see FIG. 42 [22]) while the first control signal FIRC₅ remains at a high level (see FIG. 42 [16]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3). On the other hand, though the row address latch signal generating circuits 19 ₇ is fed with the low-level block selecting signal BS₇₄₄ only while the high-level reversed row address higher-bit signal /RAD₁₀ is being fed, since the high-level first control signal FIRC₄ is not fed, the row address latch signal generating circuits 19 ₇ does not output the high-level row address latch signals RLT₇ (see FIG. 42 [24]). Similarly, the activating signal generating circuit 20 ₅, while the second control signal SECC₃ remains at a high level (see FIG. 43 [3]), generates the main-word timing control signal MTC₅ (see FIG. 43 [9]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3) and, while the third control signal THIC₃ remains at a high level (see FIG. 43 [15]), generates the sub-word activating signal SWAT₅ (see FIG. 43 [21]) and then feeds it to sub-word lines of corresponding MCA and, while two kinds of the corresponding fourth control signals FORC₁₃ and FORC₂₃ remain at a high level (see FIG. 44 [3] and [7]), generates two kinds of the SA activating signals SAAT₁₅ and SAAT₂₅ (see FIG. 44 [13] and [21]) and then feeds them to two pieces of the SAs 9 ₁₁ and 9 ₁₂ making up the fifth block by using all the blocks belonging to the bank 7 ₃ shown in FIG. 2. On the other hand, though the activating signal generating circuits 20 ₇ is fed with the low-level block selecting signals BS₇₄₄ only while the high-level reversed row address higher-bit signal /RAD₁₀ is supplied, since high-level second control signals SECC₄, high-level third control signals THIC₄ and high-level fourth control signals FORC₁₄ and FORC₂₄ are not supplied, the activating signal generating circuits 20 ₆ and 20 ₈ do not output the high-level main-word timing control signal MTC₇, high-level sub-word activating signal SWAT₇ and high-level SA activating signals SAAT₁₇ and SAAT₂₇ (see FIG. 43 [11] and [23] and FIG. 44 [15] and [23]).

While the first block is activated by all blocks belonging to the bank 7 ₁, the fourth block is activated by all blocks belonging to the bank 7 ₂ and the fifth block is activated by all blocks belonging to the bank 7 ₃ described above, the control circuit 3, after specified time has elapsed following supply of the high-level row address higher-bit signal RAD₁₀, makes the latch signal LT₄ rise to go high (see FIG. 42 [13]) and the reversed latch signal /LT₄ simultaneously fall to go low (not shown). On the other hand, the refresh decoder 15 shown in FIG. 5, though not shown, based on the high-level refresh mode signal RM₁₀ and high-level row address higher-bit signal RAD₁₀, generates the block activating designation signal ATD₂ and feeds it to the block selecting signal generating circuits 18 ₂, 18 ₄, 18 ₆ and 18 ₈. Moreover, the high-level latch signals LT₁ to LT₃ and the low-level reversed latch signal /LT₁ and /LT₂ continue to be supplied (see FIG. 42 [10] to [12]). This causes the block selecting signal generating circuit 18 ₁, 18 ₄ and 18 ₅ to output the low-level block selecting signal BS₁₁₄ and BS₄₂₄ and BS₅₄₄ (not shown). On the other hand, in the block selecting signal generating circuit 18 ₂, though the block activating designation signal ATD₂ is supplied, since the transfer gate 87 remains in an OFF state due to the high-level latch signal LT₁ and low-level reversed latch signal /LT₁, the block selecting signal BS₂₁₄ is output as a high-level signal (not shown). In the block selecting signal generating circuit 18 ₆ shown in FIG. 27, though the block activating designation signal ATD₂ is supplied, since the transfer gate 275 remains in an OFF state due to the high-level latch signal LT₃ and low-level reversed latch signal /LT₃, the block selecting signal BS₆₄₄ is output as the high-level signal (not shown). Furthermore, the block selecting signal generating circuit 18 ₈ outputs the block selecting signal BS₈₄₄ as a low level and, while the latch signal LT₄ remains at a high level, holds the block selecting signal BS₆₄₄ as the low-level signal (not shown).

Next, the control circuit 3, after specified time has elapsed, makes the first control signal FIRC₄, second control signal SECC₄, third control signal THIC₄ and two kinds of fourth control signals FORC₁₄ and FORC₂₄ sequentially rise to go high (see FIG. 42 [17], FIG. 43 [4], [16] and FIG. 44 [4] and [8]). As a result, the row address latch signal generating circuit 19 ₉ generates the row address latch signal RLT₈ (see FIG. 42 [25]) while the first control signal FIRC₄ remains at a high level (see FIG. 42 [17]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3). Similarly, the activating signal generating circuit 20 ₈, while the second control signal SECC, remains at a high level (see FIG. 43 [4]), generates the main-word timing control signal MTC₈ (see FIG. 43 [12]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3) and, while the third control signal THIC₄ remains at a high level (see FIG. 43 [16]), generates the sub-word activating signal SWAT₈ (see FIG. 43 [24]) and then feeds it to sub-word lines of corresponding MCA and, while two kinds of the corresponding fourth control signals FORC₁₄ and FORC₂₄ remain at a high level (see FIG. 44 [4] and [8]), generates two kinds of the SA activating signals SAAT₁₈ and SAAT₂₈ (see FIG. 44 [16] and [24]) and then feeds them to two pieces of the SAs 9 ₂₁ and 9 ₂₂ making up the eighth block by using all the blocks belonging to the bank 7 ₄ shown in FIG. 2.

The control circuit 3, after having made the first control signal FIRC₁ fall to go low (see FIG. 42 [14]), by causing the third control signal THIC₁, two kinds of the fourth control signals FORC₁₁ and FORC₂₁ to fall simultaneously to go low (see FIG. 43 [13] and FIG. 44 [1] and [5]), makes both the sub-word activating signal SWAT₁ and two kinds of SA activating signals SAAT₁₁ and SAAT₂₁ simultaneously fall (see FIG. 43 [17] and see FIG. 44 [9] and [17]). Then, the control circuit 3, by making the second control signal SECC₁ fall to go low (see FIG. 43 [1]), after completion of the activation of the first block by using all blocks belonging to the bank 7 ₁, makes the latch signal LT₁ fall to go low (see FIG. 42 [10]) and the reversed latch signal /LT₁ simultaneously rise to go high (not shown). Then, the control circuit 3, after having made the first control signal FIRC₂ fall to go low (see FIG. 42 [15]), by causing the third control signal THIC₂, two kinds of the fourth control signals FORC₁₂ and FORC₂₂ to fall simultaneously to go low (see FIG. 43 [14] and FIG. 44 [2] and [6]), makes both the sub-word activating signal SWAT₄ and two kinds of SA activating signals SAAT₁₄ and SAAT₂₄ simultaneously fall (see FIG. 43 [20] and see FIG. 44 [2] and [20]). Then, the control circuit 3, by making the second control signal SECC₂ fall to go low (see FIG. 43 [2]), after completion of the activation of the fourth block by using all blocks belonging to the bank 7 ₂, makes the latch signal LT₂ fall to go low (see FIG. 42 [11]) and the reversed latch signal /LT₂ simultaneously rise to go high (not shown). Then, the control circuit 3, after having made the first control signal FIRC₃ fall to go low (see FIG. 42 [16]), by causing the third control signal THIC₃, two kinds of the fourth control signals FORC₁₃ and FORC₂₃ to fall simultaneously to go low (see FIG. 43 [15] and FIG. 44 [3] and [7]), makes both the sub-word activating signal SWAT₅ and two kinds of SA activating signals SAAT₁₅ and SAAT₂₅ simultaneously fall (see FIG. 43 [21] and FIG. 44 [13] and [21]). Then, the control circuit 3, by making the second control signal SECC₃ fall to go low (see FIG. 43 [3]), after completion of the activation of the fifth block by using all blocks belonging to the bank 7 ₃, makes the latch signal LT₃ fall to go low (see FIG. 42 [10]) and the reversed latch signal /LT₃ simultaneously rise to go high (not shown). Then, the control circuit 3, after having made the first control signal FIRC₄ fall to go low (see FIG. 42 [17]), by causing the third control signal THIC₄, two kinds of the fourth control signals FORC₁₄ and FORC₂₄ to fall simultaneously to go low (see FIG. 43 [16] and FIG. 44 [4] and [8]), makes both the sub-word activating signal SWAT₈ and two kinds of SA activating signals SAAT₁₈ and SAAT₂₈ simultaneously fall (see FIG. 43 [24] and FIG. 44 [16] and [24]). Then, the control circuit 3, by making the second control signal SECC₄ fall to go low (see FIG. 43 [4]), after completion of the activation of the eighth block by using all blocks belonging to the bank 7 ₄, makes the latch signal LT₄ fall to go low (see FIG. 42 [13]) and the reversed latch signal /LT₄ simultaneously rise to go high (not shown).

Thereafter, every time the high-level reversed row address higher-bit signal /RAD₁₀ and high-level row address higher-bit signal RAD₁₀ are supplied, by repeating the same operations as described above on latch signals LT₁ to LT₄, reversed latch signals /LT₁ to /LT₄, first control signals FIRC₁ to FIRC₄, second control signals SECC₁ to SECC₄, third control signals THIC₁ to THIC₄ and two kinds of the fourth control signals FORC₁₁ to FORC₁₄ and FORC₂₁ to FORC₂₄, a plurality of blocks is activated at the same time. Moreover, operations of writing and reading of data, of refreshing or a like are almost the same as those of the conventional DRAM and their descriptions are omitted accordingly.

Next, operations of the reliability test on the DRAM such as the analysis on defects will be briefly described by referring to FIG. 45. First, as shown in FIG. 45 [1], the control circuit 3 makes the test mode signal TM rise to go high to move the routine to the test mode. Then, the control circuit 3, as shown in FIG. 45 [2], feeds the test clock TCK to the activating circuit 4 and, at the same time, as shown in FIG. 45 [3] to [10], sequentially makes the block forcedly-activating signals BFAT₁ to BFAT₈ rise at a time of the first to eighth rise of the test clock TCK and feeds them to the activating circuit 4. This causes the row address latch signal generating circuits 19 ₁ to 19 ₈ to output the high-level row address latch signals RLT₁ to RLT₈ with timing in which the corresponding block forcedly-activating signals BFAT₁ to BFAT₈ change to go high, as shown in FIG. 45 [11] to [18]. Moreover, the activating signal generating circuits 20 ₁ to 20 ₈ output the high-level main-word timing control signals MTC₁ to MTC₈ with timing in which the corresponding block forcedly-activating signal BFAT₁ to BFAT₈ change to go high (not shown) and simultaneously the high-level sub-word activating signals SWAT₁ to SWAT₈ at a time of the first to eighth fall of the test clock TCK as shown in FIG. 45 [19] to [26]. Therefore, since all blocks making up the memory block 1 are activated at the time when the test clock TCK has fallen eighth, the reliability test such as the analysis on defects can be executed. Then, to terminate the test, as shown in FIG. 45 [1], the test mode signal TM is made to fall as shown in FIG. 45 [1]. This makes the block forcedly-activating signals BFAT₁ to BFAT₈ (see FIG. 45 [3] to [10]), row address latch signals RLT₁ to RLT₈ (see FIG. 45 [11] to [18]), sub-word activating signals SWAT₁ to SWAT₈ (see FIG. 45 [19] to [26]) and main-word timing control signals MTC₁ to MTC₈ (not shown) to simultaneously fall to go low.

Next, normal operations of the DRAM performed when the system designer sets the storage capacity at 2M bits, the number of banks at 1 and the number of rows of memory cell arrays to be refreshed at 1K will be explained by referring to FIG. 46 to FIG. 48. In this case, the memory block, if configurations shown in FIG. 2 are applied, can be made up of 2 blocks contained in the bank 7 ₁. First, the control circuit 3, as shown in FIG. 46 [1] to [3], outputs all of the capacity mode signal CM₂, bank mode signal BM₁ and refresh mode signal RM₁₀ as a high level, and all of the capacity mode signals CM₄ and CM₈, bank mode signals BM₂ and BM₄ and refresh mode signals RM_(05,) RM₂₀ and RM₄₀ as a low level (not shown). Moreover, the control circuit 3, since the number of rows of memory cell arrays to be refreshed is set at 1K, feeds the row address higher-bit signal RAD₁₀ and the reversed row address higher-bit signal /RAD₁₀ out of address signals AD supplied from outside to the activating circuit 4, however, does not feed the row address higher-bit signals RAD₁₁ and RAD₁₂ and the reversed row address higher-bit signals /RAD₁₁ and /RAD₁₂ (see FIG. 46 [4] to [9]) to the activating circuit 4. Furthermore, the control circuit 3, since it is in a normal operation, keeps the test mode signal TM and the block forcedly-activating signals BFAT₁ to BFAT₈ at a low level and does not supply the test clock TCK. The control circuit 3, after specified time has elapsed following supply of the high-level reversed row address higher-bit signal /RAD₁₀, makes the latch signal LT₁ rise to go high (see FIG. 46 [10]) and the reversed latch signal /LT₄ simultaneously fall to go low (not shown). On the other hand, the refresh decoder 15 shown in FIG. 5, though not shown, based on the high-level refresh mode signal RM₁₀ and high-level reversed row address higher-bit signal /RAD₁₀, generates the block activating designation signal ATD₁ and feeds it to the block selecting signal generating circuits 18 ₁, 18 ₃, 18 ₅ and 18 ₇. This causes the block selecting signal generating circuit 18 ₁ to output the block selecting signal BS₁₁₄ as a low level and, while the latch signal LT₁ remains at a high level, the block selecting signal BS₁₁₄ is held as the low level signal (not shown). However, since the high-level latch signals LT₂ to /LT₄ and the low-level reversed latch signals /LT₂ to /LT₄ are not supplied, the block selecting signals BS₃₂₄, BS₅₄₄ and BS₇₄₄ are output, as the low-level signal, respectively from the block selecting signal generating circuits 18 ₃, 18 ₅ and 18 ₇ only while the block activating designation signal ATD₁ is being fed, that is, only while the high-level reversed row address higher-bit signal /RAD₁₀ is being fed.

Next, the control circuit 3, after specified time has elapsed, makes the first control signal FIRC₁, second control signal SECC₁, third control signal THIC₁ and two kinds of fourth control signals FORC₁₁ and FORC₂₁ sequentially rise to go high and latches it for specified period of time (see FIG. 46 [14], FIG. 47 [1] and [13] and FIG. 48 [1] and [5]). As a result, the row address latch signal generating circuit 19 ₁ generates the high-level row address latch signal RLT₁ (see FIG. 46 [18]) while the first control signal FIRC₁ remains at a high level (see FIG. 46 [14]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3). On the other hand, though each of the row address latch signal generating circuits 19 ₃, 19 ₅ and 19 ₇ is fed respectively with each of the low-level block selecting signals BS₃₂₄, BS₅₄₄ and BS₇₄₄ only while the high-level reversed row address higher-bit signal /RAD₁₀ is being fed, since the high-level first control signals FIRC₂ to FIRC₄ are not fed, the high-level row address latch signals RLT₃, RLT₅ and RLT₇ are not output (see FIG. 46 [20] [22] and [24]). Similarly, the activating signal generating circuits 20 ₁, while the second control signals SECC₁ remains at a high level (see FIG. 47 [1]), generates the main-word timing control signals MTC₁ (see FIG. 47 [5]) and feeds them to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3) and, while the third control signals THIC₁ remains at a high level (see FIG. 47 [3]), generates the sub-word activating signals SWAT₁ (see FIG. 47 [17]) and then feeds them to the sub-word lines of the corresponding MCA and further, while the two kinds of the fourth control signals FORC₁₁ and FORC₂₁ remain at a high level (see FIG. 48 [1] and [5]), generates the two kinds of the SA activating signals SAAT₁₁ and SAAT₂₁ (see FIG. 48 [9] and [17]) and then feeds them to two SAs 9 ₁₁ and 9 ₁₂ making up the first block being equivalent to the bank 7 ₁ in FIG. 2. On the other hand, though each of the activating signal generating circuits 20 ₃, 20 ₅ and 20 ₇ is fed respectively with each of the low-level block selecting signals BS₃₂₄, BS₅₄₄ and BS₇₄₄ only while the high-level reversed row address higher-bit signal /RAD₁₀ is being fed, since the high-level second control signals SECC₂ to SECC₄, high-level third control signals THIC₂ to THIC₄ and high-level fourth control signals FORC₁₂ to FORC₁₄ and FORC₂₂ to FORC₂₄ are not fed, the high-level main-word timing control signals MTC₃, MTC₅ and MTC₇, high-level sub-word activating signals SWAT₃, SWAT₅ and SWAT₇, high-level SA activating signals SAAT₁₃, SAAT₂₃, SAAT₁₅, SAAT₁₇ and SAAT₂₇ are not output (see FIG. 47 [7] [9] [11], [19], [21] and [23], and FIG. 48 [11], [13], [15] [19] [21] and [23]).

Then, the control circuit 3, after having made the first control signal FIRC₁ fall to go low (see FIG. 46 [14]), by causing the third control signal THIC₁, two kinds of the fourth control signals FORC₁₁ and FORC₂₁ to fall simultaneously to go low (see FIG. 47 [13] and FIG. 48 [1] and [5]), makes both the sub-word activating signal SWAT₁ and two kinds of SA activating signals SAAT₁₁ and SAAT₂₁ simultaneously fall (see FIG. 47 [17] and FIG. 48 [9] and [17]). Then, the control circuit 3, by making the second control signal SECC₁ fall to go low (see FIG. 47 [1]), after completion of the activation of the first block, makes the latch signal LT₁ fall to go low (see FIG. 46 [10]) and the reversed latch signal /LT₃ simultaneously rise to go high (not shown).

Next, the control circuit 3, after specified time has elapsed following the supply of the high-level row address higher-bit signal RAD₁₀, again makes the latch signal LT₁ rise to go high (FIG. 46 [10]) and makes the reversed latch signal /LT₁ simultaneously fall to go low (not shown). On the other hand, the refresh decoder 15 shown in FIG. 5, though not shown, based on the high-level refresh mode signal RM₁₀ and high-level row address higher-bit signal RAD₁₀, generates the block activating designation signal ATD₂ and feeds it to the block selecting signal generating circuits 18 ₂, 18 ₄, 18 ₆ and 18 ₈. This causes the block selecting signal generating circuit 18 ₂ to output the block selecting signal BS₂₁₄ as a low level and, while the latch signal LT₁ remains at a high level, the block selecting signal BS₂₁₄ is held as the low level signal (not shown). However, since the high-level latch signals LT₂ to LT₄ and the low-level reversed latch signals /LT₂ to /LT₄ are not supplied, the block selecting signals BS₄₂₄, BS₆₄₄ and BS₈₄₄ are output, as the low-level signal, respectively from the block selecting signal generating circuits 18 ₄, 18 ₆ and 18 ₈ only while the block activating designation signal ATD₂ is being fed, that is, only while the high-level row address higher-bit signal RAD₁₀ is being fed (not shown).

Next, the control circuit 3, after specified time has elapsed, makes the first control signal FIRC₁, second control signal SECC₁, third control signal THIC₁, two kinds of the fourth control signals FORC₁₁ and FORC₂₁ sequentially rise to go high (FIG. 46 [14], FIG. 47 [1] and [13] and FIG. 48 [1] and [5]). This causes the row address latch signal generating circuit 19 ₂, while the first control signal FIRC₁ remains at a high level (see FIG. 46 [14]), to generate the row address latch signal RLT₂ (see FIG. 46 [19]) and then feeds it to the row decoder 10 making up the corresponding row decoder group 6 (see FIG. 3). On the other hand, though each of the row address latch signal generating circuits 19 ₄, 19 ₆ and 19 ₈ is fed respectively with each of the low-level block selecting signals BS₄₂₄, BS₆₄₄ and BS₈₄₄ only while the high-level row address higher-bit signal RAD₁₀ is being fed, since the high-level first control signals FIRC₂ to FIRC₄ are not fed, the high-level row address latch signals RLT₄, RLT₆ and RLT₈ are not output (see FIG. 46 [21] [23] and [25]). Similarly, the activating signal generating circuit 20 ₂, while the second control signal SECC₁ is at a high level (see FIG. 47 [1]), generates the main-word timing control signal MTC₂ (see FIG. 47 [6]) and then feeds it to the corresponding row decoder 10 making up the row decoder group 6 (see FIG. 3) and, while the third control signal THIC₁ is at a high level, generates the sub-word activating signal SWAT₂ (see FIG. 47 [18]) and then feeds it to the corresponding sub-word lines of the MCA and, while two kinds of the corresponding fourth control signals FORC₁₁ and FORC₂₁ are at a high level (see FIG. 48 [1] and [5]), generates two kinds of the SA activating signals SAAT₁₂ and SAAT₂₂ (see FIG. 48 [10] and [18]) and then feeds it to the two SAs 9 ₂₁ and 9 ₂₂ making up the second block being equivalent to the bank 7 ₁ in FIG. 2. On the other hand, though each of the activating signal generating circuits 20 ₄, 20 ₆ and 20 ₈ is fed respectively with each of the low-level block selecting signals BS₄₂₄, BS₆₄₄ and BS₈₄₄ only while the high-level row address higher-bit signal RAD₁₀ is being fed, since the high-level second control signals SECC₂ to SECC₄, high-level third control signals THIC₂ to THIC₄ and high-level fourth control signals FORC₁₂ to FORC₁₄ and FORC₂₂ to FORC₂₄ are not fed, the high-level main-word timing control signals MTC₄, MTC₆ and MTC₈, high-level sub-word activating signals SWAT₄, SWAT₆ and SWAT₈, high-level SA activating signals SAAT₁₄, SAAT₂₄, SAAT₁₆, SAAT₂₆, SAAT₁₈ and SAAT₂₈ are not output (see FIG. 47 [8] [10] [12], [20], [22] and [24], and FIG. 48 [12], [14], [16] [20] [22] and [24]). Then, the control circuit 3, after having made the first control signal FIRC₁ fall to go low (see FIG. 46 [14]), by causing the third control signal THIC₁, two kinds of the fourth control signals FORC₁₁ and FORC₂₁ to fall simultaneously to go low (see FIG. 47 [13] and FIG. 48 [1] and [5]), makes both the sub-word activating signal SWAT₂ and two kinds of SA activating signals SAAT₁₂ and SAAT₂₂ simultaneously fall (see FIG. 47 [18] and FIG. 48 [10] and [18]). Then, the control circuit 3, by making the second control signal SECC₁ fall to go low (see FIG. 47 [1]), after completion of the activation of the second block, makes the latch signal LT₁ fall to go low (see FIG. 46 [10]) and the reversed latch signal /LT₃ simultaneously rise to go high (not shown).

Thereafter, every time the high-level reversed row address higher-bit signal /RAD₁₀ and high-level row address higher-bit signal RAD₁₀ are supplied, by repeating the same operations as described above, the first and second blocks are activated alternately. Moreover, operations of writing and reading of data, of refreshing or a like are almost the same as those of the conventional DRAM and their descriptions are omitted accordingly

Thus, according to the embodiment of the present invention, since one memory block that can be treated as one versatile storage unit is so constructed that one MCA having a storage capacity of 1M bits and having a plurality of memory cells (512 rows×2048 columns) arranged in a matrix-like form is sandwiched between two SAs, the system designer can freely increase or decrease the number of the blocks making up the memory block according to desired storage capacity. Moreover, since activating circuits are provided which can operate in a versatile manner, irrespective of combinations of the memory capacity, the number of banks, the number of rows of memory cell arrays to be refreshed, the system designer can also perform the system design only by designating required storage capacity, the number of banks and the number of rows of memory cell arrays to be refreshed, without giving special considerations to individual circuit configuration of the DRAM. This allows the system designer to perform the system design with great ease and freedom. Furthermore, a preparation of one kind of the activating circuit which can operate in a versatile manner is all that is needed by semiconductor manufacturers, which assures shortened development period of semiconductor devices. FIG. 49 shows combinations of the storage capacity, the number of banks and the number of rows of memory cell arrays to be refreshed and relations among the capacity mode signals CM₆, CM₄ and CM₂, bank modes BM₄, BM₂ and BM₁ and refresh mode signals RM₄₀, RM₂₀, RM₁₀ and RM₀₅, that can be applied to the embodiment of the present invention. As shown in FIG. 49, the system designer can freely select any one of 19 possible combinations of the storage capacity, the number of banks and the number of rows of memory cell arrays to be refreshed.

It is apparent that the present invention is not limited to the above embodiment but may be changed and modified without departing from the scope and spirit of the invention. For example, one SA making up the block is activated in two stages by using the two kinds of SA activating signals SAAT₁₁ to SAAT₁₈ and SAAT₂₁ to SAAT₂₈ to be output by each of the activating signal generating circuits 20 ₁ to 20 ₈, however, one SA may be activated in one stage by using one kind of the SA activating signal. Moreover, each of the configuration of the row decoder 10, refresh decoder 15, block selecting signal generating circuits 18 ₁ to 18 ₈, row address latch signal generating circuits 19 ₁ to 19 ₈ and activating signal generating circuits 20 ₁ to 20 ₈ is merely one example and any configuration may be employed only if it has the same functions as those employed in the embodiment. In the above embodiment, no description of circuits to be embedded together with the DRAM is given, however, a DMAC (Direct Memory Access Controller), digital-analog converter, analog-digital converter, or a plurality of analog signal processing circuits used to process various analog signals, in addition to the CPU described in the above Related Art or digital signal processing circuits to process various digital signals may be incorporated in one semiconductor chip and they may be connected to each other through buses or signal lines therein. Also, in the above embodiment, since the MCA making up the block is so configured that a plurality of memory cells (512 rows×2048 columns) is arranged in a matrix-like form, any one of the 8M bits, 4M bits, 2M bits and 1M bits can be selected as the storage capacity, 4, 2 or 1 can be selected as the number of banks, and 4K, 2K, 1K or 512 can be selected as the number of rows of memory cell arrays to be refreshed, however, these are only examples, that is, by changing configurations of the MCA, the storage capacity, the number of banks and the number of rows of memory cell arrays to be refreshed may be set freely, and their combinations, though they are limited by configurations of the MCA, may be selected freely to some extent. Furthermore, in the above embodiment, the DRAM is employed as the memory to be embedded in the semiconductor, however, an SRAM (Static RAM) or ROM may be used as the memory, in which no refreshing is required and therefore the storage capacity and the number of banks only may be set, thus simplifying the configurations of the activating circuit 4. 

What is claimed is:
 1. A semiconductor device comprising: a memory to store various data and to be embedded in one semiconductor chip together with circuits to process various signals, wherein said memory includes a memory block in which a plurality of blocks, being corresponded to pre-set storage capacity of said memory block, made up of a memory cell array having predetermined storage capacity and being constructed of a plurality of memory cells is arranged and an activating circuit configured so as to correspond to numbers of blocks satisfying maximum settable storage capacity which outputs a variety of activating signals used to activate a plurality of said blocks making up said memory block according to pre-set storage capacity and/or numbers of banks.
 2. The semiconductor device according to claim 1, wherein said activating circuit outputs, according to pre-set storage capacity and/or numbers of banks, a block selecting signal used to select any one of blocks making up said memory block, a row address latch signal used to temporarily latch a row address decoded by a row decoder which outputs a main-word activating signal to put a main-word line corresponding to said memory cell array in a selected state based on said decoded row address, a main-word timing control signal used to control timing with which said row decoder outputs said main-word activating signal and a sub-word activating signal used to activate a sub-word line of said memory cell array making up said corresponding block, to each of a plurality of said blocks making up said memory block.
 3. The semiconductor device according to claim 1, further comprising a control circuit which generates, according to pre-set storage capacity and/or numbers of banks and based on an address supplied from outside, a latch signal used to temporarily latch said block selecting signal, a first control signal used to control timing with which said row address latch signal is output, a second control signal used to control timing with which said activating circuit outputs said main-word timing control signal, a third control signal used to control timing with which said activating circuit outputs said sub-word activating signal, a capacity mode signal corresponding to pre-set storage capacity and a bank mode signal corresponding to numbers of banks and then feeds these signals to said activating circuit with specified timing, wherein said activating circuit, based on said latch signal, said first to third control signals, said capacity mode signal and said bank mode signal, generates said various activating signals.
 4. The semiconductor device according to claim 3, wherein said control circuit, when a test on said memory is executed, generates a test mode signal used to put all banks in a test mode, a test clock being a clock used in said test mode and a block forcedly-activating signal used to forcedly activate corresponding one block contained in said blocks and feeds these signals to said activating circuit, wherein said activating circuit, based on said test mode signal, said test clock and said block forcedly-activating signal, generates said various activating signals.
 5. The semiconductor device according to claim 1, wherein said memory cell array has storage capacity of 1M bits and has said plurality of said memory cells arranged in a matrix-like manner and in 512 rows×2048 columns form and wherein storage capacity that is allowed to be set includes any one of 1M, 2M, 4M and 8M bits and numbers of banks that are allowed to be set include any one of 1, 2 and
 4. 6. A semiconductor device comprising: a dynamic random access memory to store various data and to be embedded in one semiconductor chip together with circuits to process various signals, wherein said dynamic random access memory includes a memory block in which a plurality of blocks, being corresponded to pre-set storage capacity of said memory block, made up of a memory cell array having predetermined storage capacity and being constructed of a plurality of memory cells is arranged and of first and second sense amplifiers constructed so as to sandwich said memory cell array and used to detect data read to a bit line from said memory cell making up said memory cell array and to amplify said data and an activating circuit configured so as to correspond to numbers of blocks satisfying maximum settable storage capacity which outputs a variety of activating signals used to activate a plurality of said blocks making up said memory block according to pre-set storage capacity, numbers of banks and numbers of rows of memory cell arrays to be refreshed representing numbers of rows of said memory cell arrays to be activated by one time refreshing processing.
 7. The semiconductor device according to claim 6, wherein said activating circuit outputs, according to said pre-set storage capacity, numbers of banks and numbers of rows of memory cell arrays, a block selecting signal used to select any one of blocks making up said memory block, a row address latch signal used to temporarily latch a row address decoded by a row decoder which outputs a main-word activating signal to put a main-word line corresponding to said memory cell array in a selected state, based on said decoded row address, a main-word timing control signal used to control timing with which said row decoder outputs said main-word activating signal, a sub-word activating signal used to activate a sub-word line of said memory cell array making up said corresponding block and a sense amplifier activating signal used to activate two sense amplifiers making up said corresponding block, to each of a plurality of said blocks making up said memory block.
 8. The semiconductor device according to claim 6, further comprising a control circuit which generates, according to pre-set storage capacity, numbers of banks and numbers of rows of memory cell arrays to be refreshed and based on an address supplied from outside, a latch signal used to temporarily latch said block selecting signal, a first control signal used to control timing with which said row address latch signal is output, a second control signal used to control timing with which said activating circuit outputs said main-word timing control signal, a third control signal used to control timing with which said activating circuit outputs said sub-word activating signal, a fourth control signal used to control timing with which said activating circuit outputs said sense amplifier activating signal, a capacity mode signal corresponding to pre-set storage capacity, a bank mode signal corresponding to numbers of banks, a refresh mode signal corresponding to pre-set numbers of rows of memory cell arrays to be refreshed and then feeds these signals to said activating circuit with specified timing, wherein said activating circuit, based on said latch signal, said first to fourth control signals, said capacity mode signal, said bank mode signal and said refresh mode signal, generates said various activating signals.
 9. The semiconductor device according to claim 8, wherein said activating circuit includes a refresh decoder to decode data obtained by combining higher-order bits contained in said refresh mode signal with those contained in said row address and to generate a block activating designation signal used to designate said block to be activated and a block activating section mounted in numbers corresponding to numbers of blocks satisfying maximum settable capacity, to generate, based on said latch signal, a reversed latch signal obtained by reversing said latch signal, said first to fourth control signals, said capacity mode signal, said bank mode signal and said refresh mode signal, according to pre-set storage capacity, numbers of banks and numbers of rows of memory cell arrays to be refreshed, with specified timing, said block selecting signal and generates said row address latch signal, said main-word timing control signal, said sub-word activating signal and said sense amplifier activating signal.
 10. The semiconductor device according to claim 9, wherein said block activating section includes a block selecting signal generating circuit which generates, based on said block activating designation signal, said latch signal, said reversed latch signal, said refresh mode signal and said bank mode signal, a block selecting signal used to designate said corresponding block, a row address latch signal generating circuit which generates, based on said first control signal and said block selecting signal, said row address latch signal and feeds it to corresponding one contained in said blocks and an activating signal generating circuit which generates, based on said second to fourth control signals and said block selecting signal, said sub-word activating signal and said sense amplifier activating signal and said main-word timing control signal and feeds these signals to corresponding blocks.
 11. The semiconductor device according to claim 10, wherein said control circuit, when a test on said memory is executed, generates a test mode signal used to put all banks in a test mode, a test clock being a clock used in said test mode and a block forcedly-activating signal used to forcedly activate corresponding one block contained in said blocks and feeds these signals to said activating circuit, wherein said activating circuit, based on said test mode signal, said test clock and said block forcedly-activating signal, generates said various activating signals.
 12. The semiconductor device according to claim 6, wherein said memory cell array has a storage capacity of 1M bits and has a plurality of memory cells arranged in a matrix-like manner and in 512 rows×2048 columns form and wherein storage capacity that is allowed to be set includes any one of 1M, 2M, 4M and 8M bits, numbers of banks that are allowed to be set include any one of 1, 2 and 4 and numbers of rows of memory cell arrays to be refreshed that are allowed to be set include any one of 512, 2¹⁰, 2¹¹ and 2¹². 